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lsi specification MB86617A rev.1.0 fujitsu vlsi i ieee1394 serial bus controller for dtv MB86617A lsi specification rev. 1.0 august 16, 2001
lsi specification MB86617A rev.1.0 fujitsu vlsi ii contents chapter 1 overview ................................ ................................ ................................ ................................ ................................ ............ 1 chapter 2 features ................................ ................................ ................................ ................................ ................................ .............. 2 chapter 3 chip block ................................ ................................ ................................ ................................ ................................ ......... 3 3.1. b lock d iagram ................................ ................................ ................................ ................................ ................................ .................. 4 < n ormal o peration m ode ................................ ................................ ................................ ................................ ................................ ...... 4 < a synchronous t ransmit fifo e xtended m ode ................................ ................................ ................................ ...................... 5 < a synchronous r ecei ve fifo e xtended m ode ................................ ................................ ................................ .......................... 6 3.2. f unction of e ach b lock ................................ ................................ ................................ ................................ ................................ ... 7 < phy l ayer c ontrol c ircuit ................................ ................................ ................................ ................................ ............................. 7 < link l ayer c ontrol c ircuit ................................ ................................ ................................ ................................ ........................... 7 < tsp ic i nterface ................................ ................................ ................................ ................................ ................................ .................... 7 < cp ic i nterface ................................ ................................ ................................ ................................ ................................ ...................... 7 < d ata b ridge ................................ ................................ ................................ ................................ ................................ ............................. 7 chapter 4 pin assign ment ................................ ................................ ................................ ................................ ............................... 8 4.1. p in a ssignment ................................ ................................ ................................ ................................ ................................ ..................... 9 4.2. c orresponding t able of MB86617A p in ................................ ................................ ................................ ................................ ..... 1 0 4.3. o utline d rawing of p ackage ................................ ................................ ................................ ................................ ........................ 11 chapter 5 pin functi on ................................ ................................ ................................ ................................ ................................ ... 12 5.1. ieee1394 i nterface ................................ ................................ ................................ ................................ ................................ ........... 13 5.2. i sochronous i nterface ................................ ................................ ................................ ................................ ................................ .... 14 5.4. mpu i nterface ................................ ................................ ................................ ................................ ................................ .................... 16 5.5. o ther p ins ................................ ................................ ................................ ................................ ................................ ............................ 17 5.6. p ower /gnd p in ................................ ................................ ................................ ................................ ................................ ................... 18 chapter 6 internal r egister ................................ ................................ ................................ ................................ .................... 19 chapter 7 int ernal register funct ion description ................................ ................................ ........................... 25 7.1. m ode - control r egister ................................ ................................ ................................ ................................ ................................ .. 27 7.2. flag & status r egister ................................ ................................ ................................ ................................ ................................ .... 29
lsi specification MB86617A rev.1.0 fujitsu vlsi iii 7.3. i nstruction fetch r egister ................................ ................................ ................................ ................................ ........................... 31 7.4. interrupt - factor i ndicate r egister / interrupt - mask s etting r egister ................................ ................................ ........ 32 7.5. r eceive a cknowledge i ndicate r egister ................................ ................................ ................................ ................................ . 33 7.6. a - buffer d ata p ort r eceive /t ransmit ................................ ................................ ................................ ................................ ...... 34 7.7. tsp t ransmit i nformation s e tting r egister [a] ................................ ................................ ................................ ................... 35 7.8. tsp t ransmit i nformation s etting r egister [b] ................................ ................................ ................................ ................... 37 7.9. t ransmit o ffset s etting r egister [a] ................................ ................................ ................................ ................................ ....... 39 7.10. t ransmit o ffset s etting r egister [b] ................................ ................................ ................................ ................................ ..... 40 7.11. tsp r eceive i nformation s etting r egister ................................ ................................ ................................ ........................... 41 7.12. r eceive dss p acket h eader i ndicate r egister [a]/t ransmit dss p acket h eader s etting r egister [a] ....... 44 7.13. r ece ive dss p acket h eader i ndicate r egister [b]/t ransmit dss p acket h eader s etting r egister [b] ........ 45 7.14. tsp s tatus r egister ................................ ................................ ................................ ................................ ................................ ....... 46 7.15. d ata b ridge t ransmit i nformation s etting r egister 1 [a] ................................ ................................ ............................. 48 7.16. d ata b ridge t ransmit i nformation s etting r egister 2 [a] ................................ ................................ ............................. 49 7.17. d ata b ridge t ransmit i nformation s etting r egister 3 [b] ................................ ................................ ............................. 50 7.18. d ata b ridge t ransmit i nformation s ett ing r egister 4 [b] ................................ ................................ ............................. 51 7.19. d ata b ridge r eceive i nformation s etting r egister ................................ ................................ ................................ .......... 52 7.20. t ransmit p acket l ink /s plit s etting r egister ................................ ................................ ................................ ...................... 53 7.21. l ate p acket d ecision r ange s etting r egister [a] ................................ ................................ ................................ .............. 55 7.22. l ate p acket d ecision r ange s etting r egister [b] ................................ ................................ ................................ .............. 56 7.23. r eceive i sochronous p acket h eader i ndicate r egister 1 [a] ................................ ................................ ........................ 57 7.24. r eceive i soc hronous p acket h eader i ndicate r egister 2 [a] ................................ ................................ ........................ 58 7.25. r eceive i sochronous p acket h eader i ndicate r egister 3 [b] ................................ ................................ ......................... 59 7.26. r eceive i sochronous p acket h eader i ndicate r egister 4 [b] ................................ ................................ ......................... 60 7.27. fifo r eset s etting r egister ................................ ................................ ................................ ................................ ....................... 61 7.28. d ata b ridge t ransmit /r eceive s tatus r egister [a] ................................ ................................ ................................ ........... 62 7.29. d ata b ridge t ransmit /r eceive s tatus r egister [b] ................................ ................................ ................................ ........... 65 7.30. i sochronous c hannel m onitor r egister ................................ ................................ ................................ ............................... 68 7.31. c ycle - timer - monitor i ndicate r egister ................................ ................................ ................................ ................................ . 69
lsi specification MB86617A rev.1.0 fujitsu vlsi iv 7.32. p ing t ime m onitor r egister ................................ ................................ ................................ ................................ ........................ 70 7.33. phy/link r egister /a ddress s etting r egister ................................ ................................ ................................ ................... 71 7.34. phy/link r egister a ccess p ort ................................ ................................ ................................ ................................ ............... 72 7.35. r evision i ndicate r egister ................................ ................................ ................................ ................................ .......................... 73 7.36. t ransmit cgms/tsch i ndicate r egister [a] ................................ ................................ ................................ ....................... 74 7.37. t ransmit cgms/tsch i ndicate r egister [b] ................................ ................................ ................................ ........................ 75 7.38. t ransmit cgms/tsch i ndicate s tatus r egister ................................ ................................ ................................ ................ 76 7.39. t ransmit emi/oe s etting r egister ................................ ................................ ................................ ................................ .......... 78 chapter 8 phy /ink register functi on description ................................ ................................ ................................ 80 8.1. phy/link r egister t able ................................ ................................ ................................ ................................ .............................. 81 8.2. p hysical register #00 ( read ) ................................ ................................ ................................ ................................ ......................... 83 8.3. p hysical register #01 ( read / write ) ................................ ................................ ................................ ................................ ............ 84 8.4. p hysical register #02 ( read ) ................................ ................................ ................................ ................................ ......................... 85 8.5. p hysical register #03 ( read ) ................................ ................................ ................................ ................................ ......................... 86 8.6. p hysical register #04 ( read / write ) ................................ ................................ ................................ ................................ ............ 87 8.7. p hysical register #05 ( read / wr ite ) ................................ ................................ ................................ ................................ ............ 88 8.8. p hysical register #07, 08, 09 ( read ) ................................ ................................ ................................ ................................ ........... 90 8.9. p hysical register #0a, 0b, 0c ( read / write ) ................................ ................................ ................................ ............................ 91 8.10. p hysical register #0d, 0e, 0f ( read / write ) ................................ ................................ ................................ ........................... 92 8.11. p hysical register #10 ( read ) ................................ ................................ ................................ ................................ ....................... 93 8.12. p hysical register #11, 12, 13 ( read ) ................................ ................................ ................................ ................................ ......... 94 8.13. p hysical register #14, 15, 16 ( read ) ................................ ................................ ................................ ................................ ......... 95 8.14. p hysical r egister #17, 18, 19, 1a, 1b, 1c, 1d, 1e ( read / write ) ................................ ................................ ....................... 96 8.15. l ink register #00 ( read / write ) ................................ ................................ ................................ ................................ ................... 97 8.16. l ink register #01 ( read / write ) ................................ ................................ ................................ ................................ ................... 98 8.17. l ink register #02 ( read / write ) ................................ ................................ ................................ ................................ ................... 99 8.18. l ink register #03 ( read / write ) ................................ ................................ ................................ ................................ ................. 100 chapter 9 instructio n ................................ ................................ ................................ ................................ ................................ 101 9.1. i nstruction c ode t able ................................ ................................ ................................ ................................ .............................. 102
lsi specification MB86617A rev.1.0 fujitsu vlsi v 9.2. d escription of e ach i n struction ................................ ................................ ................................ ................................ ............... 103 chapter 10 interrupt ................................ ................................ ................................ ................................ ................................ ..... 106 10.1. i nterrupt - factor i ndicator r egister & interrupt - mask s etting r egister ................................ ............................. 107 10.2. i nterrupt ................................ ................................ ................................ ................................ ................................ .......................... 108 10.3. d escription of i nterrupt ................................ ................................ ................................ ................................ ............................ 109 chapter 11 operation ................................ ................................ ................................ ................................ ................................ ... 112 11.1. i nitialization ................................ ................................ ................................ ................................ ................................ ................ 113 11.2. s elf - id p acket r eceiving ................................ ................................ ................................ ................................ ......................... 114 11.2.1 s elf - id packet receive at bus reset process ................................ ................................ ................................ ............. 115 11.2.2 self - id packet receive after transmitting ping packet ping ................................ ................................ ................ 118 11.3. a synchronous p acket t ransmitting ................................ ................................ ................................ ................................ . 120 1 1.4. a synchronous p acket r eceiving ................................ ................................ ................................ ................................ ......... 122 11.5. i sochronous p acket t ransmitting ................................ ................................ ................................ ................................ ..... 125 11.6. i sochronous p acket r eceiving ................................ ................................ ................................ ................................ ............. 128 chapter 12 system co nfiguration ................................ ................................ ................................ ................................ ... 130 12.1. r ecommended c onnection for 1934 p ort ( for one port ) ................................ ................................ .......................... 131 12.2. r ecommended c onnection for c able p ower s upply ................................ ................................ ................................ .. 132 12.3. r ecommended c onnection for b uild - in pll l oop f ilter ................................ ................................ ......................... 133 12.4. c onfiguration of f eedback c ircuit at c rystal o scillator ................................ ................................ ................... 134
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 1 chapter 1 overview this chapter explains the overview of MB86617A. MB86617A is fujitsu ? s ieee1394 serial bus controller based on both ieee1394 standard (ieee std. 1394 - 1995) and p1394.a standard draft (rev.2.0). this MB86617A has three ports for network under the 1394 cable environment, differential transceiver, and comparator, and the transfer data rate supports s400. mb8 6617a integrates phy and link layers into single - chip, and plans for degression of component side product and saving power consumption. MB86617A has two exclusive ports (one is the combined use for receiving a message of interface for dv) for mpeg2 and ds s data transfer, and performs isolating and packeting of header and data department with these two ports automatically. this function is suited for maintaining continuum of transfer.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 2 chapter 2 features this chapter explains the features of MB86617A. > compliant with ieee1394 high performance serial bus standard and p1394.a standard draft > integrates phy and link layers into single - chip > 1394 port number : 3 ports > transfer data rate : s100, s200, s400 > on - chip pll (corresponding to crystal osci llator) : generate internal clock > 4k byte x 2 channels isochronous transmit and receive data buffer > 256byte asynchronous exclusive buffer for transmit/receive > auto isolating and packeting for received header and data of packet > two exclusive ports f or isochronous transfer (8 bit bus) > loading interface with copy protection lsi (8 bits i/o) > generating and checking function for 32bit crc > 6 - pin cable supported > power supply system : 3.3v size - d battery > package : lqfp - 176 (fpt - 176p - m03)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 3 chapte r 3 chip block this chapter explains the MB86617A block diagram and the function of each block. 3.1. block diagram 3.2. function of each block
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 4 3.1. block diagram MB86617A block diagram is shown below. < < normal operation mode fig.3.1.1 block diagram - normal operation mode - 1394 interface (port 0) tpa0 xtpa0 tpb0 xtpb0 tpbias0 1394 interface (port 1) tpa1 xtpa1 tpb1 xtpb1 tpbias1 1394 interface (port 2) tpa2 xtpa2 tpb2 xtpb2 tpbias2 phy/ link layer control circuit cp ic interface fifo (2kb yte) fifo (2kbyte ) asynch transmit exclusive fifo (256 byte) asynch transmit exclusive fifo (256 byte) tsp ic interface fifo (2kbyte) fifo (2kbyte) asynch transmit packet process host interface asynch transmit packet process data bridge
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 5 < < asynchronous transmit fifo extended mode fig.3.1.2 block diagram - asynchronous transmit fifo extended mode - 1394 interface (port 0 ) tpa0 xtpa0 tpb0 xtpb0 tpbias0 1394 interface (port 1) tpa1 xtpa1 tpb1 xtpb1 tpbias1 1394 interface (port 2) tpa2 xtpa2 tpb2 xtpb2 tpbias2 phy/ link layer control circuit cp ic interface fifo (2kbyte) fi fo (2kbyte ) asynch transmit exclusive fifo (256 byte) asynch transmit exclusive fifo (256 byte) tsp ic interface fifo (2kbyte) fifo (2kbyte) asynch transmit packet process host interface asynch transmit packet process data bridge
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 6 < < asynchronous r eceive fifo extended mode fig.3.1.3 block diagram - asynchronous receive fifo extended mode - 1394 interface (port 0) tpa0 xtpa0 tpb0 xtpb0 tpbias0 1394 interface (port 1) tpa1 xtpa1 tpb1 xtpb1 tpbias1 1394 interface (port 2) tpa2 xtpa2 tpb2 xtpb2 tpbias2 phy/ link layer control circuit cp ic interface fifo (2kbyte) fifo (2kbyte ) asynch transmit exclus ive fifo (256 byte) asynch transmit exclusive fifo (256 byte) tsp ic interface fifo (2kbyte) fifo (2kbyte) asynch transmit packet process host interface asynch transmit packet process data bridge
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 7 3.2. function of each block this section explains the function of each block for MB86617A. < < phy layer contro l circuit this circuit is for the physical layer of ieee 1394 with the following functions . > asynchronous transfer is supported under cable environment. > maximum transfer data rate : 393.216mbit/sec . > with three ports for transceiver/receiver : trans fer ieee1394 packet > with bus monitor, initial performance for occurring bus reset, speed signaling, arbitration, encode/decode : transfer/receive data < < link layer control circuit this circuit generates standard packet for ieee1394, controls transfer , and performs the following functions. > generates and checks 32 bit crc for header and data of packet. > activates cycle master function with integrated 32 bit cycle timer register < < tsp ic interface this tsp ic interface has two exclusive ports with the following functions for transmitting/receiving tsp ic, mpeg2 - ts and dss data, and receiving dv data. > adds time stamp to both mpeg2 - ts and dss data. > outputs received data just when the value of time stamp (sph) and cycle timer is matched with each other. > integrated transmit/receive (dual purpose) fifo for transferring isochronous by 2k byte x 2 channels. < < cp ic interface this interface adds the copy information to cp ic so as to correspond to copy protect. < < data bridge this data bridge pac kets mpeg2 - ts, dss, and dvc, and re - builds the receiving data. at data transmission, this section adds isochronous packet header and cip header, and connects/separates source packet when transmitting 2ch, it connects isochronous packet. at data receipt, i t deletes isochronous packet header and cip header, restores by unit of source packet. when receiving 2ch, it separates isochronous packet and divide them to each fifo. > integrated transmit/receive (dual purpose) fifo for transferring isochronous by 2k by te x 2 channels.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 8 chapter 4 pin assignment this chapter explains the pin assignment and table of pin function of MB86617A. 4.1. pin assignment 4.2. corresponding table of MB86617A pin 4.3. outline drawing of package
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 9 4.1. pin assignment the following diagram shows the MB86617A pin assignment. 88 85 80 75 70 65 60 55 50 45 vss vdd pmode linkon pwr3 pwr2 pwr1 vdd vss avss avdd tpbias0 tpa0 xtpa0 tpb0 xtpb0 avdd avss avss avdd tpbias1 tpa1 xtpa1 tpb1 xtpb1 avdd avss avss avdd tpbias2 tpa2 xtpa2 tpb2 xtpb2 avdd avss selioa ierra tsda0 tsda1 tsda2 tsda3 vss vdd tsda4 tsda5 tsda6 tsda7 tsvala tscgmsa tssynca tsclka vss vdd vss vdd vss vdd xreset mode1 mode0 xcs xwr(xds) xrd(r/xw) ale xint dreq xdack vdd vss d15 d14 d13 d12 d11 d10 d9 d8 vdd vss ad7 ad6 ad5 ad4 ad3 ad2 ad1 d0 test1 test2 vss xi vdd xo avss avdd fil rf avss avdd ro cps seltspa dssclka vdd vss tsclkb tssyncb tscgmsb tsvalb tsdb7 tsdb6 tsdb5 tsdb4 vdd vss tsdb3 tsdb2 tsdb1 tsdb0 ierrb seliob seltspb dssclkb vdd vss test3 test4 xfp xilwre xiv iclk vdd vss test5 test6 a7 a6 a5 a4 a3 a2 a1 test7 vdd vss 1 5 10 15 20 25 30 35 40 44 1 32 130 125 120 115 110 105 100 95 90 89 1 33 135 140 145 150 155 160 165 170 175 176 mb86617 fpt-176p-m03
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 10 4.2. corresponding table of MB86617A pin the following table shows the corresponding items of MB86617A pin. pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name pin no. i/o pin name 1 i xre set 45 - avss 89 133 o seltspa 2 i mode1 46 - avdd 90 134 i dssclka 3 i mode0 47 i/o xtpb2 91 135 - vdd 4 i xcs 48 i/o tpb2 92 136 - vss 5 i xwr(xds) 49 i/o xtpa2 93 137 i/o tsclkb 6 i xrd(r/xw) 50 i/o tpa2 94 138 i tssyncb 7 i ale 51 o t pbias2 95 139 i tscgmsb 8 o xint 52 - avdd 96 - vdd 140 i/o tsvalb 9 o dreq 53 - avss 97 - vss 141 i/o tsdb7 10 i xdack 54 - avss 98 142 i/o tsdb6 11 - vdd 55 - avdd 99 143 i/o tsdb5 12 - vss 56 i/o xtpb1 100 144 i/o tsdb4 13 i/o d15 57 i/o t pb1 101 145 - vdd 14 i/o d14 58 i/o xtpa1 102 146 - vss 15 i/o d13 59 i/o tpa1 103 147 i/o tsdb3 16 i/o d12 60 o tpbias1 104 148 i/o tsdb2 17 i/o d11 61 - avdd 105 - vdd 149 i/o tsdb1 18 i/o d10 62 - avss 106 - vss 150 i/o tsdb0 19 i/o d9 63 - avss 107 151 o ierrb 20 i/o d8 64 - avdd 108 152 o seliob 21 - vdd 65 i/o xtpb0 109 153 o seltspb 22 - vss 66 i/o tpb0 110 154 i dssclkb 23 i/o ad7 67 i/o xtpa0 111 155 - vdd 24 i/o ad6 68 i/o tpa0 112 156 - vss 25 i/o ad5 69 o tpbias0 113 157 i/o test3 26 i/o ad4 70 - avdd 114 158 i/o test4 27 i/o ad3 71 - avss 115 - vdd 159 o xfp 28 i/o ad2 72 - vss 116 - vss 160 o xilwre 29 i/o ad1 73 - vdd 117 i/o tsclka 161 i xiv 30 i/o d0 74 i pwr1 118 i/o tssynca 162 i iclk 31 i/o test1 75 i pwr2 119 i/o tscgmsa 163 - vdd 32 i/o test2 76 i pwr3 120 i/o tsvala 164 - vss 33 - vss 77 o linkon 121 i/o tsda7 165 i/o test5 34 i xi 78 i pmode 122 i/o tsda6 166 i/o test6 35 - vdd 79 123 i /o tsda5 167 i a7 36 i/o xo 80 124 i/o tsda4 168 i a6 37 - avss 81 125 - vdd 169 i a5 38 - avdd 82 126 - vss 170 i a4 39 o fil 83 127 i/o tsda3 171 i a3 40 o rf 84 128 i/o tsda2 172 i a2 41 - avss 85 - vdd 129 i/o tsda1 173 i a1 42 - avdd 86 - vss 130 i/o tsda0 174 i/o test7 43 o ro 87 13 1 o ierra 175 - vdd 44 i cps 88 132 o selioa 176 - vss
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 11 4.3. outline drawing of package this section shows the outline drawing of MB86617A package (lqfp - 176).
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 12 chapter 5 pin function this chapter explains the MB86617A pin function. 5.1. iee e1394 interface 5.2. isochronous (tsp - ic,dv - ic) interface 5.4. mpu interface 5.5. other pins 5.6. power/gnd pin
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 13 5.1. ieee1394 interface this section explains the pin function of ieee1394 interface. signal name i/o function tpa 0 i/o i/o pin of tpa + (plus) signal on cable port 0 xtpa0 i/o i/o pin of tpa - (minus) signal on cable port 0 tpb0 i/o i/o pin of tpb + (plus) signal on cable port 0 xtpb0 i/o i/o pin of tpb - (minus) signal on cable port 0 tpa1 i/o i/o pin of tpa + (plus) signal on cable port 1 xtpa1 i/o i/o pin of tpa - (minus) signal on cable port 1 tpb1 i/o i/o pin of tpb + (plus) signal on cable port 1 xtpb1 i/o i/o pin of tpb - (minus) signal on cable port 1 tpa2 i/o i/o pin of tpa + (plus) signal on cable port 2 xtpa2 i/o i/o pi n of tpa - (minus) signal on cable port 2 tpb2 i/o i/o pin of tpb + (plus) signal on cable port 2 x tp b2 i/o i/o pin of tpb - (minus) signal on cable port 2 tpb ias0 o output pin of reference voltage for common voltage on cable port 0 tpbias1 o output pi n of reference voltage for common voltage on cable port 1 tpbi as2 o output pin of reference voltage for common voltage on cable port 2
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 14 5.2. isochronous interface this section explains the pin function of isochronous interface. signal name i/o funct ion tsvalida i/o i.o pin for indicating effective data period of ts packet (on port a) ? h ? active signal tssynca i/o input/output pin for indicating leading data of ts packet (on port a) ? h ? active signal tsclka i/o on transmitting: sync clock input p in for input data of ts packet on receiving : sync clock output pin for output data of ts packet (switchable either 6.144mhz or 3.072mhz) tsda7 - 0 i/o i/o pin for ts packet data (on port a) tscgmsa i serial input pin for cgms and tsch information (on port a) effective for 8 clocks since tssynca input signal rising selioa o output pin for switching i/o on port a outputs ? l ? at transmitting and ? h ? at receiving seltspa o output pin for switching output device from port a tsvalidb i/o i.o pin for indi cating effective data period of ts packet (on port b) ? h ? active signal tssyncb i/o input/output pin for indicating leading data of ts packet (on port b) ? h ? active signal tsclkb i/o on transmitting: sync clock input pin for input data of ts packet on receiving : sync clock output pin for output data of ts packet (switchable either 6.144mhz or 3.072mhz) tsdb7 - 0 i/o i/o pin for ts packet data (on port b) tscgmsb i serial input pin for cgms and tsch information (on port b) effective for 8 clocks si nce tssynca input signal rising seliob o output pin for switching i/o on port b outputs ? l ? at transmitting and ? h ? at receiving seltspb o output pin for switching output device from port b iclk i clock input pin from dv - ic xilwre o output pin for sig nal to be allowed accessing to isochronous - fifo asserted by completing reception of data for one source packet ? l ? active signal xiv i input signal for enable signal of isochronous data output isochronous - fifo data to data output pin while this signal in active. switch data synchronizing with rise edge of iclk xfp o output pin of time stamp trigger signal ? l ? active signal
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 15 ierra o output pin for noticing error of receive data (on port a) ? h ? active signal ierrb o output pin for noticing error of rec eive data (on port b) ? h ? active signal dssclka i clock input pin for dss data (27mhz) dssclkb i clock input pin for dss data (27mhz)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 16 5.4. mpu interface this section explains the pin function of mpu interface. signal name i/o function a7 ? 1 i a ddress input pin for selecting internal register available only when selecting non - multi mode when selecting multiplex mode, set this signal in fixed ? l ? d15 - 8,0 ad7 ? 1 i /o data i/o pin corresponding to address input signal when selecting multiplex mo de xcs i chip enable input pin for this device xrd(r/w) i 80 system mode: read out strobe input pin for this device 68 system mode: input pin for controlling read out/write for this device xwr(xds) i 80 system mode: strobe input pin for writing into thi s device 68 system mode: input pin of xds signal to be output with data bus in available ale i input pin of ale signal to be output with its address in available when selecting multiplex mode when selecting non - multiplex mode, set this signal in fixed ? l ? dreq o output pin of dma transfer requiring signal for dmac xdack i input pin of dma allowance signal from dmac xint o output pin for interruption request
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 17 5.5. other pins this section explains the pin function like internal pll. signal name i /o function xreset i input signal for resetting signal when operating with cable supply power, set this pin to ? l ? . mode1 mode0 i this pin is used for setting operating mode of mpu. this device is operated as follows depending on the setting of mode1 and mo de0 pins; ? 00 ? input: tx1940 mode ? 01 ? input: mb90f574 mode ? 10 ? input: 80 system non - multiplex mode ? 11 ? input: 68 system non - multiplex mode xo i/o xi i exterior type crystal connecting pin for oscillator circuit (24.576mhz) rf o connect t o gnd through 5.1 k w register. fil o exterior type filter circuit connecting pin for internal pll ro o connect to gnd through 5.1 k w register. cps i power supply input pin from ieee1394 cable detect cable supply power 0 to 33v (requiring of lowering/div iding voltage) pmode i criterion pin for inputting power ? l ? input : operate with power supplying through ieee1394 cable ? h ? input: operate with system power pwr3 - 1 i setting pin got power_class of self - id packet to be transmitted when operating with supply power through cable. note) the power_class of the self_id packet to be sent when operating under the system power does not use this pin, but follows the setting of pwr bit (bit2 to 0) of physical register#4. linkon o output pin for detecting link - o n packet receive output ? h ? when receiving link - on packet under operating with supply power through ieee1394 cable. when pmode becomes ? h ? , ? l ? is output. with the pmode in ? h ? , the output of this pin is not changed. if not using this pin, set this pin as open one. test1 - 7 i/o this pin is for test. use this pin as open one.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 18 5.6. power/gnd pin this section explains the power/gnd pin. signal name i/o function vdd - 3.3v digital power pin vss - digital ground pin avdd - 3.3v analog power pin avss - analog ground pin
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 19 chapter 6 internal register this chapter explains the MB86617A internal register. note that the access of internal register is applied only 16 bits access. write read address (hex) register name register name 00 mode - con trol mode - control 02 (reserved) flag & status 04 instruction - fetch instruction - fetch 06 interrupt - mask setting [a] interrupt indicate [a] 08 interrupt - mask setting [b] interrupt indicate [b] 0a (reserved) receive acknowledge 0c a - buffer data port tr ansmit a - buffer data port receive 0e (reserved) (reserved) 10 tsp transmit information setting [a ] tsp transmit information setting [a ] 12 tsp transmit information setting [b ] tsp transmit information setting [b ] 14 transmit offset setting [a] (upper) transmit offset setting [a] (upper) 16 transmit offset setting [a] (lower) transmit offset setting [a] (lower) 18 transmit offset setting [b] (upper) transmit offset setting [b] (upper) 1a transmit offset setting [b] (lower) transmit offset setting [b] (lower) 1c tsp receive information setting tsp receive information setting 1e transmit dss packet header setting [a] (most significant) receive dss packet header setting [a] (most significant)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 20 write read address (hex) register name register name 2 0 transmit dss packet header setting [a] (upper) receive dss packet header setting [a] (upper) 2 2 transmit dss packet header setting [a] (medium) receive dss packet header setting [a] (medium) 2 4 transmit dss packet header setting [a] (lower) receive dss packet header setting [a] (lower) 2 6 transmit dss packet header setting [a] (least significant) receive dss packet header setting [a] (least significant) 2 8 transmit dss packet header setting [b] (most significant) receive dss packet header setting [b] (most significant) 2 a transmit dss packet header setting [b] (upper) receive dss packet header setting [b] (upper) 2 c transmit dss packet header setting [b] (medium) receive dss packet header setting [b] (medium) 2 e transmit dss packet header setting [b ] (lower) receive dss packet header setting [b] (lower) 3 0 transmit dss packet header setting [b] (least significant) receive dss packet header setting [b] (least significant) 3 2 (reserved) tsp status 3 4 data bridge transmit information setting 1 [a] da ta bridge transmit information setting 1 [a] 3 6 data bridge transmit information setting 2 [a] data bridge transmit information setting 2 [a] 3 8 data bridge transmit information setting 3 [b] data bridge transmit information setting 3 [b] 3a data bridge transmit information setting 4 [b] data bridge transmit information setting 4 [b] 3c data bridge receive information setting data bridge receive information setting 3e transmit packet concatenate/split setting transmit packet concatenate/split setting 4 0 late packet criterion range setting [a] late packet criterion range setting [a] 4 2 late packet criterion range setting [b] late packet criterion range setting [b] 4 4 (reserved) receive isochronous packet header indicate 1 [a] 4 6 (reserved) receive is ochronous packet header indicate 2 [a] 4 8 (reserved) receive isochronous packet header indicate 3 [b] 4 a (reserved) receive isochronous packet header indicate 4 [b] 4 c fifo reset fifo reset 4 e (reserved) data bridge transmit/receive status [a]
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 21 write read add ress (hex) register name register name 5 0 (reserved) data bridge transmit/receive status [b] 5 2 (reserved) isochronous channel monitor 1 5 4 (reserved) i sochronous channel monitor 2 5 6 (reserved) isochronous channel monitor 3 5 8 (reserved) isochronous channel monitor 4 5a (reserved) cycle - time - monitor (upper) 5c (reserved) cycle - time - monitor (lower) 5e (reserved) ping time monitor 6 0 phy/link register address setting phy/link register address setting 6 2 phy/link register access port phy/link register access port 6 4 (reserved) revision indicate register (upper) 6 6 (reserved) revision indicate register (lower) 6 8 (reserved) (reserved) 6 a (reserved) (reserved) 6 c (reserved) (reserved) 6 e (reserved) (reserved) 7 0 (reserved) (rese rved) 7 2 (reserved) (reserved) 7 4 (reserved) (reserved) 7 6 (reserved) (reserved) 7 8 (reserved) (reserved) 7a (reserved) (reserved) 7c (reserved) (reserved) 7e (reserved) (reserved)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 22 write read address (hex) register name register name 8 0 (res erved) transmit cgms/tsch indicate [a] 8 2 (reserved) transmit cgms/tsch indicate [b] 8 4 transmit cgms/tsch indicate status transmit cgms/tsch indicate status 8 6 transmit emi/oe setting transmit emi/oe setting 8 8 (reserved) (reserved) 8 a (reserved) (re served) 8 c (reserved) (reserved) 8 e (reserved) (reserved) 9 0 (reserved) (reserved) 9 2 (reserved) (reserved) 9 4 (reserved) (reserved) 9 6 (reserved) (reserved) 9 8 (reserved) (reserved) 9a (reserved) (reserved) 9c (reserved) (reserved) 9e (reserved) (reserved) a 0 (reserved) (reserved) a 2 (reserved) (reserved) a 4 (reserved) (reserved) a 6 (reserved) (reserved) a 8 (reserved) (reserved) a a (reserved) (reserved) a c (reserved) (reserved) a e (reserved) (reserved)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 23 write read address (hex) regi ster name register name b 0 (reserved) (reserved) b 2 (reserved) (reserved) b 4 (reserved) (reserved) b 6 (reserved) (reserved) b 8 (reserved) (reserved) ba (reserved) (reserved) bc (reserved) (reserved) be (reserved) (reserved) c 0 (reserved) (reserved ) c 2 (reserved) (reserved) c 4 (reserved) (reserved) c 6 (reserved) (reserved) c 8 (reserved) (reserved) c a (reserved) (reserved) c c (reserved) (reserved) c e (reserved) (reserved) d 0 (reserved) (reserved) d 2 (reserved) (reserved) d 4 (reserved) (rese rved) d 6 (reserved) (reserved) d 8 (reserved) (reserved) da (reserved) (reserved) dc (reserved) (reserved) de (reserved) (reserved)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 24 write read address (hex) register name register name e 0 (reserved) (reserved) e 2 (reserved) (reserved) e 4 (res erved) (reserved) e 6 (reserved) (reserved) e 8 (reserved) (reserved) ea (reserved) (reserved) ec (reserved) (reserved) ee (reserved) (reserved) f 0 (reserved) (reserved) f 2 (reserved) (reserved) f 4 (reserved) (reserved) f 6 (reserved) (reserved) f 8 (reserved) (reserved) f a (reserved) (reserved) f c (reserved) (reserved) fe (reserved) (reserved)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 25 chapter 7 internal register function description this chapter explains the details of the internal register of MB86617A. 7.1. mode - control register 7.2. flag & status register 7.3. instruction fetch register 7.4. interrupt - factor indicate register/interrupt - mask setting register 7.5. receive acknowledge indicate register 7.6. a - buffer data port receive/transmit 7.7. tsp transmit information set ting register [a] 7.8. tsp transmit information setting register [b] 7.9. transmit offset setting register [a] 7.10. transmit offset setting register [b] 7.11. tsp receive information setting register 7.12. transmit dss packet header setting register [a] 7.13. transmit dss packet header setting register [b] 7.14. tsp status register 7.15. data bridge transmit information setting register 1 [a ] 7.16. data bridge transmit information setting register 2 [a ] 7.17. data bridge transmit information sett ing register 3 [b] 7.18. data bridge transmit information setting register 4 [b] 7.19. data bridge receive information setting register 7.20. transmit packet link/split setting register 7.21. late packet decision range setting register [a] 7.22. late packet decision range setting register [b] 7.23. receive isochronous packet header indicate register 1 [a] 7.24. receive isochronous packet header indicate register 2 [a]
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 26 7.25. receive isochronous packet header indicate register 3 [b] 7.26. receive isochronous packet header indicate register 4 [b] 7.27. fifo reset setting register 7.28. data bridge transmit/receive status register [a] 7.29. data bridge transmit/receive status register [b] 7.30. isochronous channel monitor register 7.31. cycle - ti mer - monitor indicate register 7.32. ping time monitor register 7.33. phy/link register/address setting register 7.34. phy/link register/access port 7.35. revision indicate register 7.36. transmit cgms/tsch indicate register [a] 7.37. transmit cgms/ts ch indicate register [b] 7.38. transmit cgms/tsch indicate status register 7.39. transmit emi/oe setting register
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 27 7.1. m ode - control register mode - control register is the register that performs the relative setting of various operation mode of this lsi . ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 h r/w - - - - cps soft reset clk off s - i d store cp_ trhrou gh - - - iso - fi fo no clr asyn - fifos el send/re c tsp stand - by cp stand - by initial v alue ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? ?0? ? 1 ? ? 0 ? ? 1 ? ? 1 ? ? 1 ? bit bit name action value function read - always indicate ? 0 ? . 15 - 12 reserved write - always write in ? 0 ? . 11 cps soft reset read/ write - phy/link is reset by writing ? 0 ? afte r writing ? 1 ? (not automatic clear) note: 1) perform read modify write so as not to re - write other bit. 2) write ? 0 ? after 500 ns minimum passed after writing ? 1 ? . 0 not stop clock for providing to tsp i/f, cp i/f and data bridge. 10 clk off read/ write 1 stop clock for providing to tsp i/f, cp i/f and data bridge when pmode input terminal is in ? h ? . 0 deletes self - id packet in spite of receiving it during bus reset. 9 s - id store note 1 ) read / write 1 in case of receiving self - id packet during bu s reset process, this bit stores 512 byte at maximum accompanying with both asynchronous receive fifo and asynchronous transmit fifo. 0 enable cp - ic interface.(needs external cp ic) 8 cp_through read/ write 1 disable cp - ic interface. cp - ic interface i s internally by passed. 0 tssynca and tssyncb signals are neccesary to detect the first byte of the input data to tsp interface. 7 sync_in read/ write 1 tssynca and tssyncb signals are not neccesary to detect the first byte of the input data to tsp in terface. 0 tssynca and tssyncb signals are not asserted when the data is outputted from tsp interface. 6 sync_out read/ write 1 tssynca and tssyncb signals are asserted when the data is outputted from tsp interface. read 0 always indicate ? 0 ? . 5 reserved write 0 always write in ? 0 ? . 0 clears receive isochronous - fifo when bus reset occurred. 4 iso - fifo no clr read/ write 1 does not clear isochronous - fifo when bus reset occurred.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 28 bit bit name action value function 0 uses 2k byte fifo on link i/f side of bridge for isochronous transmit/receive. 3 asyn - fifo sel read/ writ e 1 uses 2k byte fifo on link i/f side of bridge for asynchronous transmit/receive. 0 uses 2k byte fifo for asynchronous transmit with asyn - fifo se l ( bit3) ? 1 ? . 2 send/rec read / write 1 uses 2k byte fifo for asynchronous receive with asyn - fifo sel ( bit3) ? 1 ? . 0 activates tsp - ic i/f terminal output. 1 tsp stand - by read / write 1 disables tsp - ic i/f terminal output , and brings it in high impedance status. 0 activates cp i/f terminal output. 0 cp stan d - by read / write 0 disables cp i/f terminal output, and brings it in high impedance status. note 1) refer to ? self - id packet receive operation ? for the internal operation flow and read - out flow of with this bit set at ? 1 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 29 7.2. f lag & s tatus register flag & status register indicates the status of this lsi and data access inquiries. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h r ipc b usy tran r eady t ran b usy iso cycle a - tx - buff empty a - rx - buff empty - - - - - sleep data req recv busy cmstr int initial value ?0? ?0? ?0? ?0? ?1? ?1? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ?0? ?0? ?0? ?0? ?0? bit bit name action value function 0 indicates that r eceipt of instruction is available. 15 ipc busy read 1 indicates that receipt of instruction is not available. 0 indicates that bus reset or forced sleep is being executed, and transmit/receive of packet is unavailable. 14 tran ready read 1 indicates that bus rese t is completed and forced sleep is not being executed, and transmit/receive of packet is available. 0 indicates that packet transmit is not being executed or in the process of packet receive addressed to this node. 13 tran busy read 1 indicates that p acket transmit is being executed or in the process of packet receive addressed to this node. 0 indicates that isochronous cycle is not being executed. 12 iso cycle read 1 indicates that isochronous cycle is being executed by transmit or receive of cyc le start packet. 0 indicates that asynchronous transmit specific buffer is not empty. 11 a - tx - buff e mpty read 1 indicates that asynchronous transmit specific buffer is empty. 0 indicates that asynchronous receive specific buffer i s not empty. 10 a - rx - buff empty read 1 indicates that asynchronous receive specific buffer is empty. 9 ? 5 reserved read 0 always indicate ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 30 bit bit name action value function 0 indicates that the device is not in forced sleep. 4 sleep read 1 indicates that the device is in forced sleep by accepting ? start sleep ? (01h) instruction. 0 indicates that no data is stored in async receive specific buffer. 3 data req read 1 indicates that data is stored in async receive specific buffer. 0 indicates that packet receive is not in busy mode. 2 recv busy note 2 ) read 1 indicates that packet receive is in busy mode due to receipt of asynchronous packet and self - id packet. 0 indicates that node is not the cycle master now. 1 cmstr read 1 node is the cycle master now. 0 interrupt indicate register does not have interrupt. 0 int read 1 interrupt indicate register has interrupt. note 1) ieee1394 block is in internal reset status until integrated pll is locked after turning the power on. phy layer and link la yer do not operate during this period. note 2) in case that asynchronous packet addressed to this node is received with this bit indicate ? 1 ? , it transmits ? ack busy x ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 31 7.3. i nstruction - fetch register instruction - fetch register is the register that wri tes in instructions for this lsi, and consists of the instruction code and operand. refer to ? chapter 9 instruction ? for each instruction code and operand code. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bit 1 bit 0 04h r / w instruction code operand initial value ?00 h? ?00 h? bit bit name action value function 15 - 8 instruction code read / write - specify each instruction code. 7 - 0 operand read / write - specify required operand for each instru ction code. write ? 0 ? into all b its for instructions without operand. note) before writing in instruction for this register, read out ipc busy bit (bit15) of ? 7.2. f lag & status register ? , and confirm that the ipc busy value is ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 32 7.4. i nterrupt - facto r indicate register/i nterrupt - mask setting register interrupt - factor indicate register is the register that indicates interrupt reported by this lsi. refer to ? chapter 10 interrupt ? for measure against and details of each bit and interrupt factor. interru pt - mask setting register is the register that controls mask of each interrupt factor generated by this lsi. ad r / bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r interrupt - factor 06h w interrupt - mask r interrupt - factor 0 8 h w interrupt - mask initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0 ? ?0? ?0? ?0? bit bit name action value function 0 indicate that interrupt factors are not generated. interrupt - facto r read 1 indicate that interrupt factors are generated. after reading out this register, clear to ? 0 ? automatically. 0 do not mask interrupt factors. 15 - 0 inter rupt - mask write 1 mask interrupt factors. interrupt factors masked by setting of this register are neither stored in interrupt indicate register nor assert int signal.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 33 7.5. receive acknowledge indicate register rece ive acknowledge indicate register is the register that indicates received acknowledge packet addressed to itself. read out this register after interrupt report of ? asynchronous packet send ? . ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 a h r - - - - - - - - receive ack - code receive ack - parity initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0 h? ?0 h? bit bit name action value function 15 - 8 reserved read - always indicate ? 0 ? . 7 - 4 re ceive acknowledge - co de read - indicate code of received acknowledge packet addressed to it. (msb: bit7, lsb: bit5) 3 - 0 receive acknowledge - par ity read - indicate parity of received acknowledge packet addressed to it . (msb: bit3, lsb: bit0) note) in ca se of not receiving acknowledge within specified time, this register indicates ? 00h ? and reports interrupt of ? acknowledge missing ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 34 7.6. a - buffer data port receive/transmit this integrated register is the buffer access port for both async receive speci fic buffer and async transmit specific one. read data is able to be read out ieee1394 packet data in the order received. (msb: 1 st read) write data is transmitted as ieee1394 packet data in the order written in. (msb: 1 st write) ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r a sync receive specific buffer data 0 c h w async transmit specific buffer data initial value undefined bit bit name action value function a sync receive speci fic buffer data read - read out port of asynchronous receive specific buffer. (msb: bit15, lsb: bit0) 15 - 0 async transmit specific buffer data write - write in port of asynchronous transmit specific buffer. (msb: bit15, lsb: bit0)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 35 7.7. tsp transmit informa tion setting register [a] tsp transmit information setting register [a] is the register that makes settings for transmit packet processed by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10 h r/ w tx start - a tx end - a tx select - a set ts - id - a tx form - a input dss size - a emi select - a set emi - a 27m count - a port mask - a initial value ? 0 ? ? 0 ? ? 0 ? ? 00 h ? ? 0 ? ?0? ? 0 ? ? 00 b ? ? 0 ? ? 0 ? bit bit name action value function 0 automatically clears when transmit process is started with bridge - ach after setting at ? 1 ? . 15 tx start - a read/ write 1 starts transmit processing with bridge - ach. 0 automatically clears when transmit process is stopped by bridge - ach afte r setting at ? 1 ? . 14 tx end - a read/ write 1 stops transmit process by bridge - ach. 0 outputs ? l ? to seltspa output terminal. 13 tx select - a read/ write 1 outputs ? h ? to seltspa output terminal. 12 - 7 set ts - id - a read/ write - set tsch classification id to be stored at f ifo of bridge - ach. (msb: bit1 2 , lsb: bit 7 ) 0 processes transmit data as mpeg2 - ts. 6 tx form - a read/ write 1 processes transmit data as dss packet. 0 processes transmit dss packet as 140 byte. 5 input dss size - a read/ write 1 processes transmit ds s packet as 130 byte.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 36 bit bit name action value function 0 selects cgms information input from tsp - ic as emi information to be output to cp - ic. 4 emi select - a read/ write 1 selects setting value of set emi - a (bit3 to 2) as emi information to be ou tput to cp - ic. 3 - 2 set emi - a read/ write - set emi information to be output to cp - ic. valid only when emi select - a (bit4) is ? 1 ? . (msb: bit 3 , lsb: bit 2 ) 0 does not insert internal 27 mhz counter value to system clock count ran ge of dss packet header. 1 27m count - a read/ write 1 inserts internal 27 mhz counter value to system clock count range of dss packet header. 0 does not mask port a input of tsp - ic interface. read in input data from port a at transmit. 0 port mask - a read/ write 1 masks port a input of tsp - ic interface. does not read in input data from port a at transmit.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 37 7.8. tsp transmit information setting register [b] tsp transmit information setting register [b] is the register that makes settings for transmit packet processed by bri dge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 h r/ w tx start - b tx end - b tx select - b set ts - id - b tx form - b input dss size - b emi select - b set emi - b 27m count - b port mask - b i nitial value ? 0 ? ? 0 ? ? 0 ? ? 00 h ? ? 0 ? ?0? ? 0 ? ? 00 b ? ? 0 ? ? 0 ? bit bit name action value function 0 automatically clears when transmit process is started with bridge - bch after setting at ? 1 ? . 15 tx start - b read/ write 1 starts transmit process with br idge - bch. 0 automatically clears when transmit process is stopped by bridge - bch after setting at ? 1 ? . 14 tx end - b read/ write 1 stops transmit process by bridge - bch. 0 outputs ? l ? to seltspb output terminal. 13 tx select - b read/ write 1 outputs ? h ? to seltspb output terminal. 12 - 7 set ts - id - b read/ write - set tsch classification id to be stored at fifo of bridge - bch. (msb: bit1 2 , lsb: bit 7 ) 0 processes transmit data as mpeg2 - ts packet. 6 tx form - b read/ write 1 processes transmit data as dss packet. 0 processes transmit dss packet as 140 byte. 5 input dss size - b read/ write 1 processes transmit dss packet as 130 byte.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 38 bit bit name action value function 0 selects cgms information input from tsp - ic as em i information to be output to cp - ic. 4 emi select - b read/ write 1 selects setting value of set emi - a (bit3 to 2) as emi information to be output to cp - ic. 3 - 2 set emi - b read/ write - set emi information to be output to cp - ic. valid only when emi select - a (bit4) is ? 1 ? . (msb: bit 3 , lsb: bit 2 ) 0 does not insert internal 27 mhz counter to system clock count range of dss packet header. 1 27m count - b read/ write 1 inserts internal 27 mhz counter to system clock count range of dss packet header. 0 do es not mask port b input of tsp - ic interface. reads in input data from port a at transmit. 0 port mask - b read/ write 1 masks port b input of tsp - ic interface. does not read in input data from port a at transmit.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 39 7.9. transmit offset setting register [a] transmit offset sett ing register [a] is the register that sets offset value added to cycle - time - monitor value. its aim is to generate source packet header (time - stamp) added to transmit packet processed by bridge - ach. (max. 32 ms) time - stamp value is generated on the basis o f cycle - time - monitor value at input of first byte of source packet from tsp - ic. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14h r/w reserved transmit - offset - a (high) 1 6 h r /w transmit - offs et - a (low) initial value ?00 00 h? bit bit name action value function read - always indicate ? 0 ? . 15 - 4 (high) reserved write - always write in ? 0 ? . 3 - 0 (high) 15 - 12 (low) set value to be added to cycle - count ra nge of cycle - time - monitor. setting range is 0h to ffh. (unit=125 m s). 11 - 0 transmit - offset - a read / write - set value to be added to cycle - offset range of cycle - time - monitor. setting range is 0h to c00h. (unit=1/24.576 mhz).
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 40 7.10. transmit offset setting register [b] transmit off set setting register [b] is the register that sets offset value added to cycle - time - monitor value its aim is to generate source packet header (time - stamp) added to transmit packet processed by bridge - bch. (max. 32 ms) time - stamp value is generated on the basis of cycle - time - monitor value at input of first byte of source packet from tsp - ic. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18h r/w reserved transmit - offset - b (high) 1 a h r /w transm it - offset - b (low) initial value ?00 00 h? bit bit name action value function read - always indicate ? 0 ? . 15 - 4 (high) reserved write - always write in ? 0 ? . 3 - 0 (high) 15 - 12 (low) set value to be added to cycle - c ount range of cycle - time - monitor. setting range is 0h to ffh. (unit=125 m s). 11 - 0 transmit - offset - b read / write - set value to be added to cycle - offset range of cycle - time - monitor. setting range is 0h to c00h. (unit=1/24.576mhz).
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 41 7.11. tsp receive information setting register ts p receive information setting register performs the setting for outputting received packet to tsp - ic ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1c h r/ w tv2b tv1b - - output dss size - b dv - en dss - en ts - e n tv2a tv1a - - output dss size - a tcl ksl cmp sel tsc mp initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ?0? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function 0 does not output packet received by bridge - bch to port b of tsp - ic i/f. 15 tv2b read/ write 1 outputs packet received by bridge - bch to port b of tsp - ic i/f. 0 does not output packet received by bridge - bch to port a of tsp - ic i/f. 14 tv1b read/ write 1 outputs packet received by bridge - bch to port a of tsp - ic i/f . read - always indicates ? 0 ? . 13 - 12 reserved write - always write in ? 0 ? . 0 outputs dss packet received by bridge - bch, with dss packet header attached, to tsp - ic in unit of 140 byte. 11 output dss size - b read/ write 1 outputs dss packet receive d by bridge - bch, without attachment of dss packet header, to tsp - ic in unit of 130 byte. removed dss packet header is stored at receive dss packet header indicate register [b]. 0 deletes received data and reports fmt error when dv dat a is received. iso packet header and cip header are indicated in register. 10 dv - en read/ write 1 allows receiving dv data. 0 deletes received data and reports fmt error when dss data is received. iso packet header and cip header are indicated in regi ster. 9 dss - en read/ write 1 allows receiving dss data.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 42 bit bit name action value function 0 deletes received data and reports fmt error when mpeg2 - ts data is received. iso packet header and cip header are indicated in register. 8 ts - en read/ write 1 allows receivi ng mpeg2 - ts data. 0 does not output the packet received by bridge - ach to port b of tsp - ic i/f. 7 tv2a read/ write 1 outputs the packet received by bridge - ach to port b of tsp - ic i/f. 0 does not output the packet received by bridge - ach to port a of tsp - ic i/f. 6 tv1a read/ write 1 outputs the packet received by bridge - ach to port a of tsp - ic i/f. read - always indicates ? 0 ? . 5 - 4 reserved write - always write in ? 0 ? . 0 outputs dss packet with dss packet header received by bridge - bch to tsp - ic in unit of 140 byte. 3 output dss size - read/ write 1 outputs dss packet without dss packet header received by bridge - ach to tsp - ic in unit of 130 byte. removed dss packet header is stored at receive dss packet header indicate register [a]. 0 outputs received data to tsp - ic in synchronization with 6.144 mhz tsclk. 2 tclksl read/ write 1 outputs received data to tsp - ic in synchronization with 3.072 mhz tsclk. 0 outputs to port a when tscmp (bit0) is ? 1 ? . 1 cmpsel read/ write 1 outputs to port b when tscmp (bit0) is ? 1 ? . 0 does not merge packet received by ach and bch. 0 tscmp read/ write 1 outputs to one tsp - ic after merging packets received by ach and bch. note 1) do not set tv2b (bit15), tv1b (bit14), and dv1b (bit12) to ? 1 ? simultane ously. note 2) do not set tv2a (bit7), tv1a (bit6), and dv1a (bit4) to ? 1 ? simultaneously. note 3) do not set tv2b (bit15) and tv2a (bit7) to ? 1 ? simultaneously. note 4) do not set tv1b (bit14) and tv1a (bit6) to ? 1 ? simultaneously. note 5) do not set ? 1 ? to tv2b (bit15), tv1b (bit14), tv2a (bit7) and tv1a(bit6) when tscmp (bit0) is set to ? 1 ? . note 6) fmt error is reported when receiving data format other than dv - en (bit10), dss - en (bit9) and ts - en (bit8) regardless of their settings.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 43 register setting va lue and selection of output port are shown in the table below. bit 15 bit 14 bit 7 bit 6 bit 1 bit 0 receive status tv2b tv1b tv2a tv1a cmp sel ts cmp tsp - ic i/f port a tsp - ic i/f port b 0 0 0 1 0 0 processing - ach receive data - 0 0 1 0 0 0 - processing - ach receive data 0 1 0 0 0 0 processing - bch receive data - 1ch receive 1 0 0 0 0 0 - processing - bch receive data 1 0 0 1 0 0 processing - ach receive data processing - bch receive data 0 1 1 0 0 0 processing - bch receive data processin g - ach receive data 0 0 0 0 0 1 processing - ach+bc h receive data - 2ch receive 0 0 0 0 1 1 - processing - ach+bc h receive data
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 44 7.12. receive dss packet header indicate register [a]/transmit dss packet header setting register [a] receive dss packet header indi cate register [a] indicates dss packet header range of dss packet received by bridge - ach. transmit dss packet header setting register [a] sets dss packet header range of dss packet received by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rx - si f - a rx - system clock count - a(high) 1eh w tx - sif - a tx - system clock count - a(high) r rx - system clock count - a(low) rx - e f - a reserved 20h w tx - system clock count - a(low) tx - e f - a reserved r reserved 22h w reserved r reserved 24h w reserved r reserved 26h w reserved initial value ? 0000 h ? bit bit name active value function rx - sif - a read - indicates sif range of received dss packet header. 15 (1eh) tx - sif - a write - w rite in sif ra nge of transmits dss packet header. rx - system clock count - a read - indicate system clock count range of received dss packet header. (msb: 1eh - bit14 , lsb: 20h - bit8 ) 14 - 0 (1eh) 15 - 8(20h) tx - system clock count - a write - w rite in system clock count ran ge of transmit dss packet header. (msb: 1eh - bit14 , lsb: 20h - bit8 ) rx - ef - a read - indicates ef range of received dss packet header. 7(20h) tx - ef - a write - w rite in ef range of transmits dss packet header. read - indicates reserved range of received dss packet header. 6 - 0(20h) 15 - 0(22h) 15 - 0(24h) 15 - 0(26h) reserved write - w rite in reserved range of transmit dss packet header.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 45 7.13. receive dss packet header indicate register [b]/transmit dss packet header setting register [b] receiv e dss packet header indicate register [b] indicates dss packet header range of dss packet received by bridge - bch. transmit dss packet header setting register [b] sets dss packet header range of dss packet received by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rx - si f - b rx - system clock count - b (high) 28h w tx - sif - b tx - system clock count - b (high) r rx - maximum bit rate - b (low) rx - e f - b reserved 2ah w tx - maximum bit rate - b (lo w) tx - e f - b reserved r reserved 2ch w reserved r reserved 2eh w reserved r reserved 30h w reserved initial value ? 0000 h ? bit bit name action value function rx - sif - b read - indicates sif range of receive dss packet header. 15 (28h) tx - sif - b write - write in sif range of transmit dss packet header. rx - system clock count - b read - indicate system clock count range of receive dss packet header. (msb: 28h - bit1 4 , lsb: 2ah - bit 8 ) 14 - 0 (28h) 15 - 8(2ah) tx - system clock count - b write - write in sy stem clock count range of transmit dss packet header. (msb: 28h - bit1 4 , lsb: 2ah - bit 8 ) rx - ef - b read - indicates ef range of received dss packet header. 7(2ah) tx - ef - b write - write in ef range of transmit dss packet header. read - indicates reserved range of receive dss packet header. 6 - 0 (2ah) 7 - 0 (2ch) 15 - 0 (2eh) 15 - 0 (30h) reserved write - write in reserved range of transmit dss packet header.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 46 7.14. tsp status register tsp status register indicates status of tsp - ic i/f. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 32 h r cg chg - b ts chg - b no 47h - b tsp fifof ull - b tsp fifo emp - b tx - len gth - err - b - - cg chg - a ts chg - a no 47h - a tsp fifo full - a tsp fifo emp - a tx - len gth - err - a - - initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ?0? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function 0 indicates that cgms information input from port b of tsp ic i/f is not changed. 15 cg chg - b read 1 indicates that cgms information corresponding to tsch classification id of same type input from port b of tsp ic i/ f is changed. clears to ? 0 ? by lead of this register. 0 indicates that ts classification id input from port b of tsp ic i/f is not changed. 14 ts chg - b read 1 indicates that tsch classification id input from port b of tsp ic i/f is not consistent with tsch classification id (10h - bit12 to 7 set ts - id - a or 12h - bit12 to 7 set ts - id - b) to be stored to fifo. clears to ? 0 ? by lead of this register. 0 indicate s that synchronization byte of received mpeg2 - ts input from cp - ic by bridge - bch is 47h 13 no 47h - b read 1 indicates that synchronization byte of received mpeg2 - ts input from cp - ic by bridge - bch is not 47h clears to ? 0 ? by lead of this register. 0 indicates that fifo on tsp ic i/f side of bridge - bch is not full. 12 tsp fifo full - b read 1 indicates that fifo on tsp ic i/f side of bridge - bch is full. 0 indicates that fifo on tsp ic i/f side of bridge - bch is not empty. 11 tsp fifo emp - b read 1 indicates that fifo on tsp ic i/f side of bridge - bch is empty. 0 indicates that transmit data length input from tsp ic i/f is normal. 10 tx - length - err - b read 1 indicates that transmit data length input from tsp ic i/f is not consistent with specified format data length. deletes transmit data without writing into fifo. clears to ? 0 ? by lead of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 47 bit bit name active value function 9~8 reserved read - always indicate ? 0 ? . 0 indicates that cgms information input from port a of tsp ic i/f is not changed. 7 cg chg - a read 1 indicates that cgms information input from port a of tsp ic i/f is changed. clears to ? 0 ? by lead of this register. 0 indicates that ts classification id input from port a of tsp ic i/f is not changed. 6 ts chg - a read 1 indicates th at tsch classification id input from port b of tsp ic i/f is not consistent with tsch classification id (10h - bit12 to 7 set ts - id - a or 12h - bit12 to 7 set ts - id - b) to be stored to fifo. clears to ? 0 ? by lead of this register. 0 indicates th at synchronization byte of received mpeg2 - ts input from cp - ic by bridge - bch is 47h 5 no 47h - a read 1 indicates that synchronization byte of received mpeg2 - ts input from cp - ic by bridge - bch is not 47h clears to ? 0 ? by lead of this register. 0 in dicates that fifo on tsp ic i/f side of bridge - ach is not full. 4 tsp fifo full - a read 1 indicates that fifo on tsp ic i/f side of bridge - ach is full. 0 indicates that fifo on tsp ic i/f side of bridge - ach is not empty. 3 tsp fifo emp - a read 1 indicates that fifo on tsp ic i/f side of bridge - ach is empty. 0 indicates transmit data length input from tsp ic i/f is normal. 2 tx - length - err - a read 1 indicates transmit data length input from tsp ic i/f is not consistent with specified format data length. deletes transmit data without writing into fifo. clears to ? 0 ? by lead of this register. 1 - 0 reserved read - always indicate ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 48 7.15. data bridge transmit information setting register 1 [a] data bridge transmit information setting register 1 [a] is the register th at sets cip header range added to transmit packet processed by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 34 h r/w tx sid - a tx dbs - a tx fn - a initial value ? 00 h ? ? 00 h ? ? 00 b ? bit bit name action value function 15 - 10 tx sid - a read/ write - write in sid range of transmit cip header. (msb: bit1 5 , lsb: bit 1 0) 9 - 2 tx dbs - a read/ write - write in dbs range of transmit cip header. (msb: bit 9 , lsb: bit 2 ) mpeg2 - ts at transmit: ? 00000110 ? b dss at transmit: ? 00001001 ? b 1 - 0 tx fn - a read/ write - write in fn range of transmit cip header. (msb: bit 1 , lsb: bit 0 ) mpeg2 - ts at transmit: ? 11 ? b dss at transmit: ? 10 ? b
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 49 7.16. data bridge transmit information setting register 2 [a] data bridge transmit information setting register 2 [a] is the register that sets cip header range, transmit channel, and speed added to transmit packet processed by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 bit 0 36 h r/w tx fmt - a tx tsf - a tx channel - a tx speed - a - initial value ? 00 ? h ? 0 ? ? 00 ? h ? 00 ? b ? 0 ? bit bit name action value function 15 - 10 tx fmt - a read/ write - write in fmt range of transmit cip header. (msb: bit1 5 , lsb: bit 1 0) mpeg2 - ts at transmit: ? 100000 ? b dss at transmit: ? 100001 ? b 9 tx tsf - a read/ write - write in tsf range of transmits cip header. 8 - 3 tx channel - a read/ write - write in channel range of transmit isochronous packet header. (msb: bit 8 , lsb: bit 3 ) 2 - 1 tx speed - a read/ write - write in transmit packet speed. (msb: bit 2 , lsb: bit 1 ) s100 at transmit: ? 00 ? b s200 at transmit: ? 01 ? b s400 at transmit: ? 10 ? b read - always indicates ? 0 ? . 0 reserved write - always writes in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 50 7.17. data bridge transmit information setting register 3 [b] data bridge transmit information setting register 3 [b] is the register that sets cip header range added to transmit packet processed by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 38 h r/w tx sid - b tx dbs - b tx fn - b initial value ? 00 h ? ? 00 h ? ? 00 b ? bit bit name action value function 15 - 10 tx sid - b read/ write - write in sid range of transmit cip header. (msb: bit1 5 , ls b: bit 1 0) 9 - 2 tx dbs - b read/ write - write in dbs range of transmit cip header. (msb: bit 9 , lsb: bit 2 ) mpeg2 - ts at transmit: ? 00000110 ? b dss at transmit: ? 00001001 ? b 1 - 0 tx fn - b read/ write - write in fn range of transmit cip header. (msb: bit 1 , ls b: bit 0 ) mpeg2 - ts at transmit: ? 11 ? b dss at transmit: ? 10 ? b
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 51 7.18. data bridge transmit information setting register 4 [b] data bridge transmit information setting register 4 [b] is the register that sets cip header range, transmit channel and speed a dded to transmit packet processed by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3a h r/w tx fmt - b tx tsf - b tx channel - b tx speed - b - initial value ? 00 ? h ? 0 ? ? 00 ? h ? 00 ? b ? 0 ? bit bit name action value function 15 - 10 tx fmt - b read/ write - write in fmt range of transmit cip header. (msb: bit1 5 , lsb: bit 1 0) mpeg2 - ts at transmit: ? 100000 ? b dss at transmit: ? 100001 ? b 9 tx tsf - b read/ write - write in tsf range of transmit cip header. 8 - 3 tx channel - b read/ write - write in channel range of transmit isochronous packet header. (msb: bit 8 , lsb: bit 3 ) 2 - 1 tx speed - b read/ write - write in transmit packet speed. (msb: bit 2 , lsb: bit 1 ) s100 at transmit: ? 00 ? b s200 at tran smit: ? 01 ? b s400 at transmit: ? 10 ? b read - always indicates ? 0 ? . 0 reserved write - always writes in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 52 7.19. data bridge receive information setting register data bridge receive information register performs the setting of receive packet. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3c h r/ rx start - b rx end - b rx channel - b rx start - a rx end - a rx channel - a initial value ? 0 ? ? 0 ? ? 00 h ? ? 0 ? ? 0 ? ? 00 h ? bit bit name action value function 0 automatically clears when receive process is executed by bridge - bch afte r setting at ? 1 ? . 15 rx start - b read/ write 1 executes receive process by bridge - bch. 0 automatically clears when receive process is stopped by bridge - bch after setting at ? 1 ? . 14 rx end - b read/ write 1 stops receive process by bridge - bch. 13~8 rx channel - b read/ write - write in isochronous packet channel to be received by bridge - bch. (msb: bit 8 , lsb: bit 3 ) 0 automatically clears when receive process is executed by bridge - ach after setting at ? 1 ? . 7 rx start - a read/ write 1 starts receive process by bridge - ach. 0 automatically clears when receive process is stopped by bridge - ach after setting at ? 1 ? . 6 rx end - a read/ write 1 stops receive process by bridge - ach. 5 - 0 rx - channel - a read/ write - write in isochronous packet channel to be received by bridge - ach (ms b: bit 5 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 53 7.20. transmit packet link/split setting register transmit packet link/split setting register is the register that sets number of link and split of source packets to be transmitted. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3e h r/w o/e select - b tx o/e - b nf5 spb spqb dbqb o/e select - a tx o/e - a nf5 spa spqa dbqa initial value ? 0 ? ? 0 ? ? 0 ? ? 000 b ? ? 00 b ? ? 0 ? ? 0 ? ?0? ? 000 b ? ? 00 b ? bit bit name action value function 0 selects odd/even value to be input from cp - ic as odd/even range of isochronous packet header to be transmitted by bridge - bch. 15 o/e select - b read/ write 1 selects tx o/e - b (bit14) setting value as odd/even range of isochronous packet header to be transmitted by bridge - bch 14 tx o/e - b read/ write - write in odd/even range of transmit isochronous packet header. valid with o/e select - b (bit15) setting value ? 1 ? , and reads in this setting value to transmit isochronous packet header. 0 executes 2sp combined transmission as fifo nfull operation when setting of 2sp separated transmission or combined transmission for less than 2sp. with more than 3 sp, executes according to setting. 13 nf5spb read/ w rite 1 executes 5 sp combined transmission at fifo f ull. 12 - 10 spqb read/ write - write in number of link of source packet processed by bridge - bch. 9 - 8 dbqb read/ write - write in number of split of source packet processed by bridge - bch. 0 selects odd/even value to be input from cp - ic as odd/even range of isochronous packet header to be transmitted by bridge - bch. 7 o/e select - a read/ write 1 selects tx o/e - b b (bit6) setting value as odd/even range of isochronous packet header to be transmitted by bridge - bch 6 tx o/e - a read/ write - write in odd/ even range of transmit isochronous packet header. valid with o/e select - b (bit7) setting value ? 1 ? , and reads in this setting value to transmit isochronous packet header.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 54 bit bit name action value function 0 executes 2sp combined transmission as fifo nfull operation when setting of 2sp separated transmission or combined transmission for less than 2sp. with more than 3 sp, executes according to setting. 5 nf5spa read/ write 1 executes 5 sp combined transmission at fifo full. 4 - 2 spqa read/ write - write in number of links for source packet processed by bridge - ach. 1 - 0 dbqa read/ write - write in number of links for source packet processed by bridge - ach. note) >spq[2:0] ----- please specify link number of source packet. valid setting values are 0 - 5. processes assuming there are no settings from microcomputer during ? 0 ? setting. when 6 - 7 are set, it is regarded to be 5 source packet link. >dbq[1:0] ---- please specify split number of source packet. ? 00 ? --- no setting from microcomputer. ? 01 ? --- 2 splits ? 1 0 ? --- 4 splits ? 11 ? --- 8 splits, 4 splits at dss > when the setting values of both spq [2:0] and dbq [1:0] are not ? 0 ? , follow the setting of spq [2:0]. when the setting values of both spq [2:0] and dbq [1:0] are ? 0 ? (no setting from microcomputer), lsi automati cally executes link process in 1 source packet unit.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 55 7.21. late packet decision range setting register [a] late packet decision range setting register [a] is the register that sets late decision range of source packet to be transmitted by bridge - ach. a d r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 h r/w late range - a initial value ? 0000 h ? bit bit name action value function 15 - 8 write in late packet decision range. setting range is 0h to ffh (unit: 125 m s). 7 - 0 late range - a read/ write - write in late packet decision range. setting range is 0h to c0h (unit: 16/24.576mhz). note) late packet decision is performed by comparing the time difference between sph (source packet header) and ctr (cycle time monitor). - transmit: packet is transmitted normally when calculation result of ? sph ? minus ? ctr ? for source packet transmitted from bridhe - ach is within the ? late range - a + ? 0000 ? h ? . if it is out of range, late packet process is perfor med. the packet concerned is deleted and transmit late is reported. set the upper 16 bit of the setting value for transmit offset setting register[a] (14h to 16h). - receive: received packet is output at the point of ? sph = ctr ? when calculation result of ? sph ? minus ? ctr ? for source packet received at bridhe - ach is within the ? late range - a + ? 0000 ? h ? (the value this register is shifted 4 bits to the left). if it is out of range, late packet process is performed. the packet concerned is deleted and receive late is reported.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 56 7.22. late packet decision range setting register [b] late packet decision range setting register [b] is the register that sets late decision range of source packet to be transmitted by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 1 2 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 42 h r/w late range - b initial value ? 0000 h ? bit bit name action value function 15 - 8 write in late packet decision range. setting range is 0h to f fh (unit: 125 m s). 7 - 0 late range - b read/ write - write in late packet decision range. setting range is 0h to c0h (unit: 16/24.576mhz). note) late packet decision is performed by comparing the time difference between sph (source packet header) and ctr (cycle time monitor). - t ransmit: packet is transmitted normally when calculation result of ? sph ? minus ? ctr ? for source packet transmitted from bridhe - bch is within the ? late range - b + ? 0000 ? h ? . if it is out of range, late packet process is performed. the packet concerned is de leted and transmit late is reported. set the upper 16 bit of the setting value for transmit offset setting register[b] (14h to 16h). - receive: received packet is output at the point of ? sph = ctr ? when calculation result of ? sph ? minus ? ctr ? for source pac ket received at bridhe - bch is within the ? late range - b + ? 0000 ? h ? (the value this register is shifted 4 bits to the left). if it is out of range, late packet process is performed. the packet concerned is deleted and receive late is reported.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 57 7.23. receiv e isochronous packet header indicate register 1 [a] receive isochronous packet header indicate register 1 [a] is the register that indicates isochronous packet header information received by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 b it 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 44 h r - - - - - - - rx emi - a rx o/e - a rx sid - a initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 00 b ? ? 0 ? ? 00 h ? bit bit name action value function 15 - 9 reserved read - always indicate ? 0 ? . 8 - 7 rx emi - a read - indicate emi range of receive isochronous packet header. (msb: bit 8 , lsb: bit 7 ) 6 rx o/e - a read - indicates odd/even range of receive isochronous packet header. 5 - 0 rx sid - a read - indicate si range of cip header of receive isochronou s packet. (msb: bit 8 , lsb: bit 3 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 58 7.24. receive isochronous packet header indicate register 2 [a] receive isochronous packet header indicate register 2 [a] is the register that indicates isochronous packet cip header information received by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 46h r - - - - rx fmt - a rx 56 - a rx stype - a initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 3f ? ? 0 ? ? 00 h ? bit bit name action value function 15 - 12 reserved read - always indicate ? 0 ? . 11 - 6 rx fmt - a read - indicate fmt range of receive isochronous packet cip header. (msb: bit 11 , lsb: bit 6 ) 5 rx 56 - a read - indicates 50/60 range of receive isochronous packet cip header when receiving dv. indicates tsf rang e of receive isochronous packet cip header when receiving mpeg2 - ts or dss. 4 - 0 rx stype - a read - indicate stype range of cip header of receive isochronous packet. (msb: bit 4 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 59 7.25. receive isochronous packet header indicate register 3 [b] receive isochronous packet header indicate register 3 [b] is the register that indicates isochronous packet header information received by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 48 h r - - - - - - rx emi - b rx o/e - b rx sid - b initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 00 b ? ? 0 ? ? 00 h ? bit bit name action value function 15 - 9 reserved read - always indicate ? 0 ? . 8 - 7 rx emi - b read - indicate emi range of receive isoch ronous packet header. (msb: bit 8 , lsb: bit 7 ) 6 rx o/e - b read - indicates odd/even range of receive isochronous packet header. 5 - 0 rx sid - b read - indicate si range of cip header of receive isochronous packet. (msb: bit 5 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 60 7.26. receive iso chronous packet header indicate register 4 [b] receive isochronous packet header indicate register 4 [b] is the register that indicates isochronous packet cip header information received by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bi t 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4a h r - - - - rx fmt - b rx 56 - b rx stype - b initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 3f ? ? 0 ? ? 00 h ? bit bit name action value function 15 - 12 reserved read - always indicate ? 0 ? . 11 - 6 rx fmt - b read - indicate fmt range of receive isochronous packet cip header. (msb: bit 11 , lsb: bit 6 ) 5 rx 56 - b read - indicates 50/60 range of receive isochronous packet cip header when receiving dv. indicates tsf range of receive isochronous packet cip header when recei ving mpeg2 - ts or dss. 4 - 0 rx stype - b read - indicate stype range of cip header of receive isochronous packet. (msb: bit 4 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 61 7.27. fifo reset setting register fifo reset setting register sets force reset of bridge and each fifo. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4c h r/w reset - b resett sp fifo - b reset brg fifo - b - - - - - reset - a reset tsp fifo - a reset brg fifo - a - - - - - initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ?0? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function 0 releases forced reset of bridge - bch. 15 reset - b read/ write 1 executes forced reset of bridge - bch. 0 releases fifo reset on tsp - ic i/f side of b ridge - bch. 14 reset tsp fifo - b read/ write 1 resets fifo on tsp - ic i/f side of bridge - bch. 0 releases fifo reset on link - i/f side of bridge - bch. 13 reset brg fifo - b read/ write 1 resets fifo on link i/f side of bridge - bch. read - always indicate ? 0 ? . 12 - 8 reserved write - always write in ? 0 ? . 0 releases forced reset of bridge - ach. 7 reset - a read/ write 1 execute forced reset of bridge - ach. 0 releases fifo reset on tsp - ic i/f side of bridge - ach. 6 reset tsp fifo - a read/ write 1 resets fifo on tsp - ic i/f of bridge - a ch. 0 releases fifo reset on link - i/f side of bridge - ach. 5 reset brg fifo - a read/ write 1 resets fifo on link i/f side of bridge - ach. read - always indicate ? 0 ? . 4 - 0 reserved write - always write in ? 0 ? . note 1) this register is not cleared a utomatically. after writing ? 1 ? , check the state and then write ? 0 ? . note 2) do not set ? 1 ? to this register during transmit/receive execution.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 62 7.28. data bridge transmit/receive status register [a] data bridge transmit/receive status register ind icates status of packet to be transmitted/received by bridge - ach. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4e h r tx busy - a rx busy - a rx 1stp - a rx emi chg - a rx o/e chg - a rx dlen err - a - tx late - a rx late - a rx 56 err - a rx stype err - a brg fifo full - a brg fifo emp - a rx dbc err - a rx cip err - a rx fmt err - a initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ?0? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function 0 indicates that bridge - ach is not in the process of transmit . indicates ? 0 ? when tx end - a (10h - bit14) is set at ? 1 ? and transmit process is stopped. 15 tx busy - a read 1 indicates that bridge - ach is in the process of transmit. indicates ? 1 ? when tx start - a (10h - bit15) is set at ? 1 ? and transmit process is started. 0 indicates that bridge - ach is not in the process of receive. indicates ? 0 ? when rx end - a (3ch - bit6) is set at ? 1 ? and receive process is stopped. 14 rx busy - a read 1 indicates that bridge - ach is in the proc ess of receive. indicates ? 1 ? when rx start - a (3ch - bit7) is set at ? 1 ? and receive process is started. 0 indicates that isochronous packet received after starting receive process is not the first packet received. 13 rx 1stp - a read 1 indicates that the first isochronous packet is received after receive process is started. clears to ? 0 ? by lead of this register. 0 indicates that emi information of received isochronous packet header is not changed. 12 rx emi chg - a read 1 indicates that emi informatio n of received isochronous packet header has changed from just former emi information of packet received by isochronous - cycle. clears to ? 0 ? by lead of this register. 0 indicates that odd/even information of received isochronous packet header is not changed. 11 rx o/e chg - a read 1 indicates that odd/even information of received isochronous packet header has changed from just former odd/even information of packet received by isochronous - cycle. clears to ? 0 ? by lead of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 63 bit bit name acti on value function 0 indicates that the data length of received packet is same as specified data length in format. 10 rx dlen - err - a read 1 indicates that the data length of received packet differs to the specified data length in the format. clears to ? 0 ? by lead of this register. 9 reserved read - always indicates ? 0 ? . 0 indicates that transmit packet is transmitted normally. 8 tx late - a read 1 indicates that transmit packet became late packet. delete packet, and not transmit. clears to ? 0 ? by le ad of this register. 0 indicates that the received packet is normal. 7 rx late - a read 1 indicates that received packet was late packet. delete packet, and not output to tsp - ic. clears to ? 0 ? by lead of this register. 0 indicates th at 50/60 range of cip header for received isochronous packet is ? 0 ? . 6 rx 56 err - a read 1 indicates that 50/60 range of cip header of received isochronous packet is ? 1 ? clears to ? 0 ? by lead of this register. 0 indicates that stype range of cip hea der of received isochronous packet is ? 00000 ? or ? 00001 ? . 5 rx stype err - a read 1 indicates that stype range of cip header of received isochronous packet is other than ? 00000 ? or ? 00001 ? . clears to ? 0 ? by lead of this register. 0 indicates that fifo on link i/f side of bridge - ach is not full. 4 brg fifo full - a read 1 indicates that fifo on link i/f side of bridge - ach is full. 0 indicates that fifo on link i/f side of bridge - ach is not empty. 3 brg fifo emp - a read 1 indicates that fifo on link i/f side of bridge - ac h is empty. 0 indicates that dbc range of cip header of received isochronous packet is normal. 2 rx dbc err - a read 1 indicates that dbc range of cip header of received isochronous packet received is not consecutive. clears to ? 0 ? by lead of this regis ter.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 64 bit bit name action value function 0 indicates that cip header of received isochronous packet is normal. 1 rx cip err - a read 1 indicates that cip header of received isochronous packet has an error. clears to ? 0 ? by lead of this register. 0 indicates that fmt range of cip header of received isochronous packet is the value allowed to be received at dv - en, dss - en or ts - en (1ch ? bit10 to 8) (dv= ? 00000 ? , mpeg2= ? 10000 ? or dss= ? 100001 ? ). 0 r x fmt err - a read 1 indicates that fmt range of cip head er of received isochronous packet is other than the value allowed to be received at dv - en, dss - en or ts - en (1ch ? bit10 to 8) (dv= ? 00000 ? , mpeg2= ? 10000 ? or dss= ? 100001 ? ). clears to ? 0 ? by reading of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 65 7.29. data bridge transmit/receive statu s register [b] data bridge transmit/receive status register [b] indicates status of packet transmitted/received by bridge - bch. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 50 h r tx busy - b rx busy - b rx 1stp - b rx emi chg - b rx o/e chg - b rx dlen err - b - tx late - b rx late - b rx 56 err - b rx stype err - b brg fifo full - b brg fifo emp - b rx dbc err - b rx cip err - b rx fmt err - b initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ?0? ? 0 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function 0 indicates that bridge - bch is not in the process of transmit . indicates ? 0 ? when tx end - b (12h - bit14) is set at ? 1 ? and transmit process is stopped. 15 tx busy - b read 1 indicates that bridge - bch is in the proc ess of transmit. indicates ? 1 ? when tx start - b (12h - bit15) is set at ? 1 ? and transmit process is started. 0 indicates that bridge - bch is not in the process of receive. indicates ? 0 ? when rx end - b (3ch - bit14) is set at ? 1 ? and receive pro cess is stopped. 14 rx busy - b read 1 indicates that bridge - bch is in the process of receive. indicates ? 1 ? when rx start - b (3ch - bit15) is set at ? 1 ? and receive process is started. 0 indicates that received isochronous packet after starting receive pr ocess is not the first receive packet. 13 rx 1stp - b read 1 indicates that the first isochronous packet is received after starting receive process. clears to ? 0 ? by lead of this register. 0 indicates that emi information of receive isochronous packe t header is not changed. 12 rx emi chg - b read 1 indicates that emi information of receive isochronous packet header has changed from just former emi information of packet received by isochronous - cycle. clears to ? 0 ? by lead of this register. 0 indicat es that odd/even information of receive isochronous packet header is not changed. 11 rx o/e chg - b read 1 indicates that odd/even information of receive isochronous packet header has changed from just former odd/even information of packet received by isochronous - cycle. clea rs to ? 0 ? by lead of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 66 bit bit name action value function 0 indicates that data length of receive packet is same as specified data length in format. 10 rx dlen - err - b read 1 indicates that data length of receive packet differs to the s pecified data length in the format. clears to ? 0 ? by lead of this register. 9 reserved read - always indicates ? 0 ? . 0 indicates that transmit packet is transmitted normally. 8 tx late - b read 1 indicates that transmit packet became late packet. dele te packet, and not transmit. clears to ? 0 ? by lead of this register. 0 indicates that received packet is normal. 7 rx late - b read 1 indicates that received packet was late packet. deletes packet, and does not output to tsp - ic. clears to ? 0 ? by lead of this register. 0 indicates that 50/60 range of cip header of received isochronous packet is ? 0 ? . 6 rx 56 err - b read 1 indicates that 50/60 range of cip header of received isochronous packet is ? 1 ? clears to ? 0 ? by lead of this register. 0 indicates that stype range of cip header of received isochronous packet is ? 00000 ? or ? 00001 ? . 5 rx stype e rr - b read 1 indicates that stype range of cip header of received isochronous packet is other than ? 00000 ? or ? 00001 ? . clears to ? 0 ? by lead of this regist er. 0 indicates that fifo on link i/f side of bridge - ach is not full. 4 brg fifo full - b read 1 indicates that fifo on link i/f side of bridge - ach is full. 0 indicates that fifo on link i/f side of bridge - ach is not empty. 3 brg fifo emp - b read 1 indicates that fifo on link i/f side of bridge - ach is empty. 0 indicates that dbc range of cip header of received isochronous packet is normal. 2 rx dbc err - b read 1 indicates that dbc range of cip header of received isochronous packet is not consecut ive. clears to ? 0 ? by lead of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 67 bit bit name action value function 0 indicates that cip header of received isochronous packet is normal. 1 rx cip err - b read 1 indicates that cip header of received isochronous packet has an error. clea red to ? 0 ? by lead of this register. 0 indicates that fmt range of cip header of received isochronous packet is the value allowed to be received at dv - en, dss - en or ts - en (1ch ? bit10 to 8) (dv= ? 00000 ? , mpeg2= ? 10000 ? or dss= ? 100001 ? ). 0 rx fmt err - b read 1 indicates that fmt range of cip header of received isochronous packet is other than the value allowed to be received at dv - en, dss - en or ts - en (1ch ? bit10 to 8) (dv= ? 00000 ? , mpeg2= ? 10000 ? or dss= ? 100001 ? ). clears to ? 0 ? by reading of this register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 68 7.30. isochronous channel monitor register isochronous channel monitor register is the register that indicates isochronous packet channel flowing through 1394 bus. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 52 h r isochronous channel monitor1 54 h r isochronous channel monitor2 56 h r isochronous channel monitor3 58 h r isochronous channel monitor4 initial value ?0000 h? bit bit name action value function 15 - 0 isochronous channel m onitor read - indicate that ? 1 ? at bit corresponding to channel number of isochronous packet flowing through 1394 bus. 52h - bit15 - 0: channel0 - channel15 54h - bit15 - 0: channel16 - channel31 56h - bit15 - 0: channel32 - channel47 58h - bit15 - 0: channel48 - channel63
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 69 7.31. c ycle - timer - monitor indicate register cycle - timer - monitor indicate register indicates value of integrated cycle - timer register. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5a h r cycle - timer - monitor ( hi ) 5c h r cycle - timer - monitor ( lo ) initial value ?0000 h? bit bit name action value function 15 - 0 cycle - timer - m onitor read - indicate value of built - in c ycle - timer register. (msb: bit15, lsb: bit0) note) this register latches the lower word ( 5a h) by reading out lower word (5ch), and releases latch by reading out upper word. to read out this register, make sure to read out in the order of 5c h ? 5a h , two as a set.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 70 7.32. ping time monitor register ping time monitor register is the register that indicates time period of transmitting request packet to receiving response packet to the request. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5e h r pi ng time monitor initial value ? 0000 h ? bit bit name action value function 15 - 0 ping time monitor read - indicate time period from transmitting request packet to receiving response packet to the request. counts by 20ns unit. (msb: bit15, lsb: bit0)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 71 7.33. phy / link register/address setting register phy/link register/address setting register is the register that sets address in order to access phy/link register indirectly. phy/link register indicated with address set by this register can be accesse d from phy/link register/access port. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 60 h r / w - - - - - - - - - phy/link - addr initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?00 h? bit b it name action value function read - always indicate ? 0 ? . 15 - 7 reserved write - always write in ? 0 ? . 6 - 0 phy/link - addr read / write - set address of phy/link register to be accessed. (msb: 6 , lsb: 0)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 72 7.34. phy / link register access port phy/link register access port is the port to access phy/link register indirectly. phy/link register indicated with address set by phy/link register/address setting register can be accessed from this port. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 b it 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 62 h r / w phy/link - data initial value ?0000 h? bit bit name action value function read - indicates phy/link register contents defined by address set by phy/link register/address setting register. (msb: 15, lsb: 0) 15 - 0 phy/link - data write - executes write in the process of register defined by this address set by phy/link register/address setting register. (msb: 15, lsb: 0)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 73 7.35. revision indicate register revision indicate register is the reg ister that indicates chip revision of this lsi. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 64h revision code (hi) 66 h r revision code (lo) initial value fixed bit bit name action value function 15 - 0 revision code read - indicate revision code. (msb: bit15, lsb: bit0)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 74 7.36. transmit cgms/tsch indicate register [a] transmit cgms/tsch indi cate register [a] indicates cgms information and identification of ts type for source packet input from port a at tsp ic i/f. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h r cgmsa - 2 tsch a - 2 cgmsa - 1 tscha - 1 initial value ? 00 b ? ? 00 h ? ? 00 b ? ? 00 h ? bit bit name action value function 15 - 14 cgmsa - 2 read - indicates cgms information for source packet indicated in tscha - 2 (bit13 to 8). (msb: bit15, lsb: bit 14 ) 13 - 8 tscha - 2 read - ind icates if id of ts type for source packet input from port a at tsp ic i/f is different from that in low bit (tscha - 1). (msb: bit1 3 , lsb: bit 8 ) 7 - 6 cgmsa - 1 read - indicates cgms information for source packet indicated in tscha - 1 (bit5 to 0). (msb: bit 7 , lsb: bit 6 ) 5 - 0 tscha - 1 read - indicates id of ts type for source packet input first from port a at tsp ic i/f (msb: bit 5 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 75 7.37. transmit cgms/tsch indicate register [b] transmit cgms/tsch indicate register [b] indicates cgms information a nd identification of ts type for source packet input from port b at tsp ic i/f. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 82 h r cgmsb - 2 tschb - 2 cgmsb - 1 tschb - 1 initial value ? 00 b ? ? 00 h ? ? 00 b ? ? 00 h ? bit bit name action value function 15 - 14 cgmsb - 2 read - indicates cgms information for source packet indicated in tschb - 2 (bit13 to 8). (msb: bit15, lsb: bit 14 ) 13 - 8 tschb - 2 read - indicates if id of ts type for source packet inpu t from port b at tsp ic i/f is different from that in low bit (tschb - 1). (msb: bit1 3 , lsb: bit 8 ) 7 - 6 cgmsb - 1 read - indicates cgms information for source packet indicated in tschb - 1 (bit5 to 0). (msb: bit 7 , lsb: bit 6 ) 5 - 0 tschb - 1 read - indicates id of ts type for source packet input first from port b at tsp ic i/f (msb: bit 5 , lsb: bit 0 )
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 76 7.38. transmit cgms/tsch indicate status register transmit cgms/tsch indicate status register indicates validity of source packet input from tsp ic i/f. ad r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 84 h r / w - - - - - act - tsc hb vld - t sc hb - 2 vld - t sc hb - 1 - - - - - act - tsc ha vld - t sc ha - 2 vld - t sc ha - 1 initial value ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? bit bit name action value function read - always indicate ? 0 ? . 15 - 11 reserved write - always write in ? 0 ? . 0 indicates that the packet indicated in cgmsb - 1 and tschb - 1 (82h - bit7 to 0) was finally in put from port b at tsp ic i/f. read 1 indicates that the packet indicated in cgmsb - 2 and tschb - 2 (82h - bit15 to 8) was finally input from port b at tsp ic i/f. 10 act - tschb write - clears to ? 0 ? by writing ? 1 ? . 0 indicates that the value indicated in cgmsb - 2 and tschb - 2 (82h - bit15 to 8) is invalid. read 1 indicates that the value indicated in cgmsb - 2 and tschb - 2 (82h - bit15 to 8) is valid. 9 vld - tschb - 2 write - clears to ? 0 ? by writing ? 1 ? . 0 indicates that the value indicated in cgmsb - 1 and tschb - 1 (82h - bit7 to 0) is invalid. read 1 indicates that the value indicated in cgmsb - 1 and tschb - 1 (82h - bit7 to 0) is valid. 8 vld - tschb - 1 write - clears to ? 0 ? by writing ? 1 ? . read - always indicate ? 0 ? . 7 - 3 reserved write - always write in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 77 bit bit n ame action value function 0 indicates that the packet indicated in cgmsa - 1 and tscha - 1 (80h - bit7 to 0) was finally input from port a at tsp ic i/f. read 1 indicates that the packet indicated in cgmsa - 2 and tscha - 2 (80h - bit15 to 8) was fina lly input from port a at tsp ic i/f. 2 act - tscha write - clears to ? 0 ? by writing ? 1 ? . 0 indicates that the value indicated in cgmsa - 2 and tscha - 2 (80h - bit15 to 8) is invalid. read 1 indicates that the value indicated in cgmsa - 2 and tscha - 2 (80h - bit15 to 8) is valid. 1 vld - tscha - 2 write - clears to ? 0 ? by writing ? 1 ? . 0 indicates that the value indicated in cgmsa - 1 and tscha - 1 (80h - bit7 to 0) is invalid. read 1 indicates that the value indicated in cgmsa - 1 and tscha - 1 (80h - bit7 to 0) is va lid. 0 vld - tscha - 1 write - clears to ? 0 ? by writing ? 1 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 78 7.39. transmit emi/oe setting register transmit emi/oe setting register sets emi information and odd/even value added to empty packet until valid data is transmitted. ad r / w bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 86 h r / w iph select - b iph emi - b iph oe - b - - - - iph select - a iph emi - a iph oe - a - - - - initial value ? 0 ? ? 00 b ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 00 b ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? ? 0 ? bit bit nam e action value function 0 sets the default value (emi= ? 00 ? , oe = ? 0 ? ) as emi information and odd/even value added to iph of empty packet until valid data is transmitted after starting transmission. 15 iph select - b read/ write 1 selects the setting val ue of iph emi - b (bit14 to 13) and iph oe - b (bit 12) as emi information and odd/even value added to iph of empty packet until valid data is transmitted after starting transmission. 14 - 13 iph emi - b read/ write - set emi information which are set in iph of empty packet transmitted from bridge - bch. valid only when iph select - b (bit15) is set to ? 1 ? . (msb: bit1 4 , lsb: bit 13 ) emi information after transmitting valid data depends on the setting of emi select - b (12h - bit4). 12 iph oe - b read/ write - set odd/even value which is set in iph of empty packet transmitted from bridge - bch. valid only when iph select - b (bit15) is set to ? 1 ? . emi information after transmitting valid data depends on the setting of o/e select - b (3eh - bit15). read - always ind icate ? 0 ? . 11 - 8 reserved write - always write in ? 0 ? . 0 sets the default value (emi= ? 00 ? , oe = ? 0 ? ) as emi information and odd/even value added to iph of empty packet until valid data is transmitted after starting transmission. 7 iph select - a read/ write 1 selec ts the setting value of iph emi - a (bit6 to 5) and iph oe - a (bit 4) as emi information and odd/even value added to iph of empty packet until valid data is transmitted after starting transmission.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 79 bit bit name action value function 6 - 5 iph emi - a read/ write - set emi information which are set in iph of empty packet transmitted from bridge - ach. valid only when iph select - a (bit7) is set to ? 1 ? . (msb: bit 6 , lsb: bit 5 ) emi information after transmitting valid data depends on the setting of emi select - a (1 0h - bit4). 4 iph oe - a read/ write - set odd/even value which is set in iph of empty packet transmitted from bridge - ach. valid only when iph select - a (bit7) is set to ? 1 ? . emi information after transmitting valid data depends on the setting of o/e select - a (3eh - bit8). read - always indicate ? 0 ? . 3 - 0 reserved write - always write in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 80 chapter 8 phy / ink register function description this chapter explains the physical register and link register that enables to access from phy/link register access p ort (address 62h) by setting phyt/link register address setting register (address 60h) in detail. 8.1. phy/link register table 8.2. physical register#00 8.3. physical register#01 8.4. physical register#02 8.5. physical register#03 8.6. physical register #04 8.7. physical register#05 8.8. physical register#07, 08, 09 8.9. physical register#0a, 0b, 0c 8.10. physical register#0d, 0e, 0f 8.11. physical register#10 8.12. physical register#11, 12, 13 8.13. physical register#14, 15, 16 8.14. physical register#17, 18, 19, 1a, 1b, 1c, 1d, 1e 8.15. link register#00 8.16. link register#01 8.17. link register#02 8.18. link register#03
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 81 8.1. phy / link register table table of physical register and link register is shown below. p hy/link addr write read 00 h (reserved) physical register #0 0 02 h physical register # 0 1 ? 04 h (reserved) physical register # 0 2 06 h (reserved) physical register # 0 3 08 h physical register # 0 4 ? 0a h physical register # 0 5 ? 0c h (reserved) physical r egister # 07 0e h (reserved) physical register # 08 10 h (reserved) physical register # 09 12 h physical register # 0a ? 14 h physical register # 0b ? 16 h physical register # 0c ? 18 h physical register # 0d ? 1ah physical register # 0e ? 1ch physical register # 0f ? 1 dh (reserved) physical register # 10 1 eh (reserved) physical register # 11 20h (reserved) physical register # 12 24h (reserved) physical register # 13 26h (reserved) physical register # 14 28h (reserved) physical register # 15 2ah (reserved) physic al register # 16
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 82 p hy/link addr write read 2ch physical register #17 ? 2eh physical register #18 ? 30h physical register #19 ? 32h physical register #1a ? 34h physical register #1b ? 36h physical register #1c ? 38h physical register #1d ? 3ah ph ysical register #1e ? 3ch link register #00 ? 3eh link register #01 ? 40h link register #02 ? 42h link register #03 ?
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 83 8.2. physical register #0 0 (read) physical register#00 is the register that indicates physical id, root status, and cable power st atus of this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 h r - - - - - - - - physical_id r ps initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?00 h? ?0? ?0? description of each bit bit bit name action value function 15 ? 8 reserved read 0 always indicate ?0? . 7 ? 2 physical_id read - indicate node no. of this node determined by self - identify during processing bus reset. (msb : 7 , lsb : 2) effective after completion of bus reset. 0 indicates that this node is not root. 1 r read 1 indicates that this node is root. 0 indicates that the supplied cable power is below specification. 0 ps read 1 indicates that the supplied cable power is over specificat ion.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 84 8.3. physical register # 0 1 (read/write) physical register#01 is the register that set s /indicate s force - root and gap - count. do not write into this register except for the case that the node is bus manager or isochronous resource manager in the envi ronment with no bus manager . phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02 h r / w - - - - - - - - rhb irb gap_count initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ?3f h? description of each bit bit bit name action value function read - always indicate ?0? . 15 - 8 reserved write - always write ?0? . 0 this node does not try to be root during next bus reset. 7 rhb note 1) read / write 1 this node tries to be root du ring next bus reset. 0 does not perform bus reset. 6 irb read / write 1 performs bus reset. automatically clears to ? 0 ? at the completion of bus reset. read - indicate current gap - count value (msb: 5 , lsb: 0) . 5 - 0 gap_count note 2) write - set gap - count value (msb: 5 , lsb: 0) . note 1) this bit is automatically set by receiving the phy configuration packet, too. note 2) this bit is automatically set by receiving the phy configuration packet, too. also, this bit value returns to initial value a t the second next bus reset.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 85 8.4. physical register # 0 2 (read) physical register#02 is the register that indicates if the extended phy register map is in existence or not, and the number of ports (3 port). phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04 h r - - - - - - - - extended - total_ports fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?7 h? ?0? ? 3 h? < < description of each bit bit bit name action value function 15 - 8 r eserved read - always indicate ?0?. 7 - 5 extended read - indicate that this node has the extended phy register map. (msb: 7 , lsb: 5) always indicate fixed value ?7 h?. 4 reserved read - always indicates ?0?. 3 - 0 total_ports read - indicate the numbe r of ports held by this node (msb: 4 , lsb: 0) . always indicate fixed value ? 3 h?.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 86 8.5. physical register # 0 3 (read) physical register#03 is the register that indicates max. transfer speed (s400) of this node. phy/ link - addr r / w bit 15 bit 14 bit 1 3 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06 h r - - - - - - - - max _speed - delay fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?1? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function 15 - 8 reserved read - always indicate ?0? . 7 - 5 max_speed read - indicate max. transfer speed supporting phy of this node (msb: 7 , lsb: 5) . always indicates fixed value ?010 b? (= s400). 4 reserved read - always indicates ?0? . 3 - 0 delay read - indicate delay value at the receive signal repeat (msb: 3 , lsb: 0 ). always indicate fixed value ? 0000 b ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 87 8.6. physical register # 0 4 (read/write) physical register#04 is the register that sets the parameter of self - id packet to be transmitted b y this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r jitter 08 h w - - - - - - - - link_a ctive c onte nder - - - pwr _class initial value ?0? ? 0? ?0? ?0? ?0? ?0? ?0? ?0? ? 1 ? ? 1 ? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 8 reserved write - always write in ? 0 ? . 7 l ink_active note 1) read / write - set l bit (link_acti ve) value of self - id packet automatically transmitted by this node with the system power on. 6 c ontender note 2) read / write - set c bit (contender) value of self - id packet automatically transmitted by this node with the system power on. rea d - indicate jitter value at receive signal repeat. (msb : 5 , lsb : 3 ) always indicates fixed value ? 000 b ? . 5 - 3 jitter write - always write in ?0?. 2 - 0 pwr _class note 3) read / write - set pwr field (power_class) value of self - id packet automatically transmitt ed by this node with the system power on. note 1) l bit value of self - id packet that is automatically transmitted by this node with the cable supply power on is always set at ? 0 ? regardless of the setting of this bit. note 2) c bit value of self - id packe t that is automatically transmitted by this node with the cable supply power on is always set at ? 0 ? regardless of the setting of this bit. note 3) pwr field value of self - id packet which is automatically transmitted by this node with the cable supply powe r on is always set at the value of pwr3 - 1 terminal regardless of the setting of this bit.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 88 8.7. physical register # 0 5 (read/write) physical register#05 is the register indicating availability of cable supply power standard and timeout detect of arbit ration state machine. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a h r / w - - - - - - - - resume _int isbr loop pwr _ fail time out port_ event enab _accel enab_ multi initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 8 reserved write - always write in ? 0 ? . 0 does not indicat e ? 1 ? at port_event bit during resume processing. 7 resume_int read / write 1 indicates ? 1 ? at port_event bit during resume processing. 0 does not perform short bus reset. 6 isbr read/ write 1 performs short bus reset. automatically clears to ? 0 ? at the completion of bus reset. 0 indicates that port connection is in a loop. read 1 indicates that port connection is in a loop. 5 loop write - clears the bit value to ? 0 ? by writing in ? 1 ? . 0 indicates that the cable supply power satisfies the standard. read 1 indicates that the cable supply power does not satisfy the standard. 4 pwr_fail write - clears the bit value to ? 0 ? by writing in ? 1 ? . 0 indicates that timeout is not detected by arbitration state machine. read 1 indicates that timeout is det ected by arbitration state machine. 3 timeout write - clears the bit value to ? 0 ? by writing in ? 1 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 89 bit bit name action value function 0 indicates that port event and resume processing have not occurred . read 1 indicates that connected, bia s, disabled, fault bit has changed when int_enable bit is set at ? 1 ? . indicates that resume processing was performed when resume_int bit is set at ? 1 ? . 2 port_event write - clears the bit value to ? 0 ? by writing in ? 1 ? . 0 disables arbitrat ion acceleration function . 1 enab_accel read / write 1 enables arbitration acceleration function. 0 disables multi - speed packet concatenation function. 0 enab_multi read / write 1 enables multi - speed packet concatenation function.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 90 8.8. physical register # 07, 08, 09 (rea d) physical register#07, 08, 09 are the registers that indicate signal condition of ieee1394 port and cable connection condition. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c h r - - - - - - - - astat - 0 bstate - 0 ch ild - 0 con nec ted - 0 - - 0e h r - - - - - - - - astat - 1 bstate - 1 ch ild - 1 con nec ted - 1 - - 10 h r - - - - - - - - astat - 2 bstate - 2 ch ild - 2 con nec ted - 2 - - initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function 15 - 8 r eserved read - always indicate ? 0 ? . 7 - 6 astat - n read - indicate tpa line state of 1394 port n ( msb : 7 , lsb : 6) . 00 = invalid 01 = ?1? 10 = ?0? 11 = ?z? 5 - 4 bstat - n read - indicate tpb line state of 1394 port n (msb : 5 , lsb : 4) . 00 = invalid 01 = ?1? 10 = ?0? 11 = ?z? 0 indicates that 1394 port n is parent port. 3 ch ild - n read 1 indicates that 1394 port n is children port. 0 indicates that cable is not connected to 1394 port n. 2 con nected - n read 1 indicates that cable is connected to 1394 port n. 1 - 0 r eserved read - always indicate ? 0 ?
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 91 8.9. physical register # 0a, 0b, 0c (read/write) physical register#0a, 0b, 0c are the registe rs that indicate bias detect condition of ieee1394 installed in this node and performs setting of enable/disable of ieee1394 port. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r bias - 0 1 2 h w - - - - - - - - - - - - - - - dis abl ed - 0 r bias - 1 14h w - - - - - - - - - - - - - - - dis abl ed - 1 r bias - 2 16h w - - - - - - - - - - - - - - - dis abl ed - 2 initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function read - always indicates ? 0 ? . 15 - 2 reserved write - always write in ? 0 ? . 0 indicates that bias voltage is not detected at 1394 po rt n. read 1 indicates that bias voltage is detected at 1394 port n. 1 bias - n write - always indicates ? 0 ? . 0 enables 1394 port n. 0 dis abled - n read / write 1 disable 1394 port n.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 92 8.10. physical register # 0d, 0e, 0f (read/write) physical register#0d, 0e, 0f are the registers that indicate maximum transfer speed of the node connected to ieee1394 port installed in this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r negotiated_speed - 0 1 8 h w - - - - - - - - - - - int_en able - 0 fault - 0 - - - r negotiated_speed - 1 1a h w - - - - - - - - - - - int_en able - 1 fault - 1 - - - r negotiated_speed - 2 1c h w - - - - - - - - - - - int_en able - 2 fault - 2 - - - initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0?? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function read - always indicates ? 0 ? . 15 - 8 reserved write - always write in ? 0 ? . read - indicate max. transfer speed between nodes connected to 1394 port n. (msb: 7, lsb: 5) 000 = s100 001 = s200 010 = s400 011 - 111 = invalid 7 - 5 negotiated_ spe ed - n write - always write in ? 0 ? . 0 does not indicate ? 1 ? at port_event bit when connected, bias, disabled, fault bit changed. 4 int_enable - n read/ write 1 indicates ? 1 ? at port_event bit when connected, bias, disabled, fault bit changed. 0 indicates that suspend or resume processing is normal. read 1 indicates that suspend or resume processing occurred error. 3 fault write - clears the bit value to ? 0 ? by writing in ? 1 ? . - always indicates ? 0 ? . 2 - 0 reserved read / write - always write in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 93 8.11. physical register # 10 (read) physical register#10 is the register that indicates c ompliance_level of this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1e h r - - - - - - - - compliance_level fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 01 h? description of each bit bit bit name action value function 15 - 8 reserved read - always indicate ? 0 ? . 7 - 0 compliance_l evel read - indicate that this node supports p1394a standard. (msb: 7 , lsb: 0) always indicate fixe value ? 01 h?.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 94 8.12. physica l register # 11, 12, 13 (read) physical register#11, 12, 13 are the registers that indicate vendor_id of this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20 h r - - - - - - - - vendor_id - hi fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 00 h? 22 h r - - - - - - - - vendor_id - mid fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 00 h? 24 h r - - - - - - - - vendor_id - lo fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 0e h? description of each bit bit bit name action value function 15 - 8 reserved read - always indicate ? 0 ? . 7 - 0 vendor_id read - indicate vendor id of fujitsu (msb: 7 , lsb: 0) . always indicate fixed value ? 00000e h?.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 95 8.13. physical register # 14, 15, 16 (read) physical register#14, 15, 16 are the registers that indicate product_id of this node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 26 h r - - - - - - - - product_id - hi fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 08 h? 28 h r - - - - - - - - product_id - mid fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 66 h? 2a h r - - - - - - - - product_id - lo fixed value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 17 h? < < description of eac h bit bit bit name action value function 15 - 8 reserved read - always indicate ? 0 ? . 7 - 0 vendor_id read - indicate product id of this chip (msb: 7 , lsb: 0) . always indicate fixed value ? 086617 h?.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 96 8.14. physical register # 17, 18, 19, 1a, 1b, 1c, 1d, 1e (read /write ) physical register#17, 18, 19, 1a, 1b, 1c, 1d, 1e are in the range of 8 bit x 8 free_ram. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2c h r / - - - - - - - - free_ram - 0 2e h r /w - - - - - - - - free_ram - 1 30 h r / - - - - - - - - free_ram - 2 32 h r / - - - - - - - - free_ram - 3 34 h r / - - - - - - - - free_ram - 4 36 h r / - - - - - - - - free_ram - 5 38 h r / - - - - - - - - free_ram - 6 3a h r / - - - - - - - - free_ram - 7 initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ? 00 h? < < description of each bit bit bit name action value function read - always indicates ? 0 ? . 15 - 8 reserved write - always write in ? 0 ? . 7 - 0 free_ram read / write - range of 8 bit x 8 free ram.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 97 8.15. link register #00 (read/write) link register#00 is the register that sets this node to operate as cycle master. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3c h r / w - - - - - - - - - - cycle master - - - - - initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ? 1 ? ?0? ?0? ?0? ? 0 ? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 6 reserved write - always write in ? 0 ? . 0 does not cycle master. read 1 operates as cycle master if it is root. 5 cycle master write - sets the value of this bit at ? 1 ? by writing in ? 1 ? . read - always indicate ? 0 ? . 4 - 0 reserved write - always w rite in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 98 8.16. link register #01 (read/write) link register#00 is the register that sets this node to perform as cycle master. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3e h r / w - - - - - - - - - - cycle master - - - - - initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ? 1 ? ?0? ?0? ?0? ? 0 ? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 6 reserved write - a lways write in ? 0 ? . 0 does not cycle master. read 1 performs as cycle master if it is root. 5 cycle master write - sets the value of this bit at ? 0 ? by writing in ? 1 ? . read - always indicate ? 0 ? . 4 - 0 reserved write - always write in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 99 8.17. link register #0 2 (read/write) link register#02 is the register that sets transfer mode of acknowledge packet transmitted by this node and disable setting of link layer. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 h r / w - - - - - - - - - - - - ack mode - link enable - initial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ?0? ? 0 ? ? 1 ? ?0? ? 1 ? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 4 r eserved write - always write in ? 0 ? . 0 at receipt of normal packet. automatically transmits acknowledge packet of ? ack_pending ? to all request packet. automatically transmits acknowledge packet of ? ack _complete ? to all response packet. automatically transmits packet. code value of acknowledge packet, automatically transmitted when error is detected, depends on the kind of error. 3 ack mode read / write 1 at receipt of normal packet. automatically transmits acknowledge packet of ? ack_pending ? to read request and lock request. automatical ly transmits acknowledge packet of ? ack_complete ? to write request packet and all response packet. code value of acknowledge packet automatically transmitted when error is detected depends on the kind of error. read - always indicates ? 0 ? . 2 reserved write - always write in ? 0 ? . 0 link layer is disabled. 1 link enable read / write 1 link layer is enabled. read - always indicates ? 0 ? . 0 reserved write - always write in ? 0 ? .
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 100 8.18. link register # 03 (read/write) link register#03 is the regis ter that performs link layer reset and initializes setting of the node. phy/ link - addr r / w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 42 h r / w - - - - - - - - - - - - - link init link reset i nitial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0?? ?0? ?0? ?0? ?0? ?0? ?0? ?0? < < description of each bit bit bit name action value function read - always indicate ? 0 ? . 15 - 2 reserved write - always write in ? 0 ? . 0 releases in itialize of link layer. 1 link init read / write 1 initializes link layer. 0 releases reset of link layer. 0 link reset read / write 1 resets link layer.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 101 chapter 9 instruction this chapter explains the instruction codes and details for respective instructions. 9.1. instruction code table 9.2. description of each instruction
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 102 9.1. instruction code table instruction name c ode operand start sleep 01 remove sleep 02 asynchronous receive 03 remove busy mode 04 send phy packet 21 asynchronous send 31 speed co de data - fifo init 6 3 fifo select code dma transmit (asynchronous ) 71 dma transmit (phy packet) 72 d ma receive 73
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 103 9.2. description of each instruction < < start sleep (01 h) this instruction changes this device into forced sleep, stops the driver/r eceiver function of 1394 port, and then changed into the status with this device ? s cable cut. also, it stops the clock to be input from integrated pll to ieee1394 block. access to each register is available. no interrupt this instruction is reported. con firm the sleep condition using sleep bit (bit4) of flag & status register (address 02h). < < remove sleep (02 h) this instruction releases this device from forced sleep condition. no interrupt to this instruction is reported. confirm the sleep conditio n release using sleep bit (bit4) of flag & status register (address 02h) < < asynchronous receive (0 3 h) this instruction reads the out data stored at async receive specific buffer. even though the receive data length does not satisfy with the quadlet unit, this instruction stores up to quadlet unit. the receive data does not have crc code and logical inverse part. < < remove busy mode (04 h) this instruction releases the busy mode set due to receiving normal asynchronous packet or self - id packet a ddressed to this node. < < send phy packet (21 h) this instruction transmits the data stored at async receive specific buffer. do not issue this instruction in case that this instruction is not bus manager node, or not isochronous resource manager no de without existence of bus manager. when packet transmit operation is completed normally, this instruction report s the interrupt of ? physical packet send ? (int25). store the transmit data at async transmit specific buffer beforehand. logical inverse part is added automatically by this device.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 104 < < asynchronous send ( 3 1 h) this instruction transmits the data stored at the async transmit specific buffer. this instruction performs the following serial actions, from access to arbitration by detecting arb - reset - gap, generation and transfer of packet, to receipt of acknowledge packet. when the performances from packet transmit to acknowledge receive are normally completed, this instruction reports interrupt of ? asynchronous packet send ? (int17). in cas e of occurring an error, it reports interrupt of error, and completes performance. s tore the transmit data at async transmit specific buffer beforehand. in case that the transmit data length does not satisfy with the quadlet unit, write in ? 0 ? until qua dlet unit. the crc code is to be added automatically. received acknowledge is indicated at receive acknowledge indicate register (address 08h). note) when destination - id is set at broadcast, it is completed without waiting for receipt of acknowledge. bit operand name meaning 7 - 2 reserved always specify ? 0 ? . 1 - 0 speed code specify transmit speed code . (msb: 1 , lsb: 0) 00 = s100 01 = s200 10 = s400 11 = (reserved) < < data - fifo init (63h) this instruction clears the con tents of buffer specified by operand. bit operand name meaning 7 - 0 fifo select code specify buffer to be cleared. (msb: 7 , lsb: 0) ?11 h? = async receive specific buffer ?12 h? = async transmit specific buffer other than above = (reserved)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 105 < < dma transmit (asynchronous) ( 71 h) this instruction writes in the transmit asynchronous packet to async transmit specific buffer using dma transmit. assert dreq signal after issuing this instruction. determine the transmit bite value by transmit data length within packet header, write in up to quadlet unit, then negate dreq signal. after completion of writing in, issue the asynchronous send instruction (31h). < < dma transmit (phy packet) ( 72 h) this instruction writes in the transmit phy packet to async transmit specific buffer using dma transfer. assert the dreq signal after issuing this instruction. negate the dreq signal after writing in 2 bites. after completion of writing in, issue the send phy packet instruction (21h). < < dm a receive ( 73 h) this instruction reads out the data stored in async receive specific fifo using dma transfer. issue asynchronous receive instruction (03h) before issuing this instruction. assert dreq signal after issuing this instruction. negate dreq s ignal when async receive specific fifo is empty.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 106 chapter 10 interrupt this chapter explains the inturrput - factors and method for interrupt - mask. 10.1. interrupt - factor indicator register & interrupt - mask setting register 10.2. interrupt 10.3. description of interrupt
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 107 10.1. interrupt - factor indicator register & interrupt - mask setting register ad r / bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r i nt 1 int 2 int 3 int 4 int 5 int 6 int 7 int 8 int 9 int 10 int 11 int 12 int 13 int 14 int 15 int 16 06h w interrupt - mask r int 17 int 18 i nt 19 int 20 int 21 int 22 int 23 int 24 int 25 int 26 int 27 int 28 int 29 int 30 int 31 int 32 0 8 h w interrupt - mask intial value ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? > interrupt - factor indicate register this register indicate the interrupt content reported by this device. do not indicate the interrupt code specified mask. do not reflect its code to xint terminal either. > interrupt - mask setting register this register masks the interrupt reported by this device. do not re port the interrupt if ? 1 ? is set for bit corresponding to interrupt factor.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 108 10.2. interrupt interrupt interrupt item int1 loop detected int2 self - id packet error int3 bus reset complete int4 bus reset detected int5 isochronous packet receive error (a - ch) int6 isochronous packet receive error (b - ch) int7 isochronous cycle too long int8 bus occupancy violation int9 asynchronous packet received int10 cpif output header is no 47h (transmit) int11 data length short error int12 data length long er ror int13 packet format error int14 header crc error int15 data crc error int16 asynchronous receive fifo full int17 asynchronous packet send int18 input cgms or tsch changed int19 acknowledge missing int20 acknowledge send int21 receive emi or od d/even changed int22 first packet received int23 cycle start packet received int24 cycle start packet send int25 physical packet send int26 extended phy packet received int27 physical configuration packet received int28 link - on packet received int2 9 self - id packet received int30 receive late occurred int31 instruction abort int32 transmit late occurred
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 109 10.3. description of interrupt each interrupt items are described below. interrupt interrupt item description int1 loop detected topology is in loop. > need to issue ? bus reset ? . occurred convention failure like physical - id did not count up each self - id packet received during self identify process. > continues to receive self - id packet after reporting interrupt, b ut reports ? bus reset complete ? (05h) interrupt. int2 self - id packet error detected logical inverse error while receiving self - id packet after sending ping packet in normal transfer mode. >delete receive packet. int3 bus reset complete this device has completed bus reset proces s and able to perform packet transfer. > all the follows, bus reset, tree identify, and self identify, are completed by this interrupt information. int4 bus reset detected reset bus reset in any of the following conditions. >detected busreset signal from other node. >received ? bus reset ? int5 isochronous packet receive error (a - ch) the following errors occurred at bridge - ach during packet receiving. >data length value differs from that specified in the format. >the value of 50/60 range at cip header is ? 1 ? at dv receiving. >the value of stype range at cip header is other than ? 00000 ? or ? 00001 ? at dv receiving. >the value of dbc range at cip header is discontinuous. >header error in cip header. >the value of fmt range at cip header is other than that all owed to be received at dv - en, dss - en or ts - en (1ch - bit10 to 8) (dv= ? 000000 ? , mpeg2 - ts= ? 100000 ? , dss= ? 100001 ? ). int6 isochronous packet receive error (b - ch) the following errors occurred at bridge - bch during packet receiving. >data length value differs f rom that specified in the format. >the value of 50/60 range at cip header is ? 1 ? at dv receiving. >the value of stype range at cip header is other than ? 00000 ? or ? 00001 ? at dv receiving. >the value of dbc range at cip header is discontinuous. >header er ror in cip header. >the value of fmt range at cip header is other than that allowed to be received at dv - en, dss - en or ts - en (1ch - bit10 to 8) (dv= ? 000000 ? , mpeg2 - ts= ? 100000 ? , dss= ? 100001 ? ).
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 110 interrupt interrupt item description int7 isochronous cycle too long isochronous cycle exceeded specified time. >informs only if this node is cycle master. int8 bus occupancy violation node occupied longer time than max_data_time. >need to issue ? bus reset ? . int9 asynchronous packet received received asynchronous packet addressed to self - node normally, and stored data at async receive specific buffer. int10 cpif output header is no 47h (transmit) header byte of source packet output from cpif at transmitting mpsg2 - ts is not ? 47h ? . >valid only when transmitting mps g2 - ts. int11 data length short error receive packet data length is shorter than data - length of packet header. int12 data length long error receive packet data length is longer than data - length of packet header. >store only data indicated by data - length value to buffer. int13 packet format error detected format error in packet received. occurred convention failure of packet format like reserved range is not ? 0 ? . >delete packet received. int14 header crc error detected crc error in the header of packet r eceived. >delete packet received. int15 data crc error detected crc error in the data range of packet received. >do not delete packet received. int16 asynchronous receive fifo full async receive specific buffer is full. >delete following packet received. int17 asynchronous packet send completed sending asynchronous packet by issu e ing instruction. int18 input cgms or tsch changed cgms or tsch information input from tsp ic i/f was not consistent with the souce packet input just before. int19 acknowledge missing not returned acknowledge packet in correspondance with asynchronous packet of non - broadcast sent from self - node within specified limit. int20 acknowledge send completed sending acknowledge packet. int21 receive emi or odd/even changed changede em i data or odd/even value of received isochronous packet. int22 first packet received received the first packet after setting receive iso channel.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 111 interrupt interrupt item description int23 cycle start packet received received cycle start packet normal ly when self node is not root > isochronous cycle starts. set iso cycle bit (bit12) of flag & status register (address 02h) at ? 1 ? simaltaneously with this interrupt report. int24 cycle start packet send completed to send cycle start packet when self node is root. int25 physical packet send completed to send physical packet. int26 extended phy packet received received extended phy packet normally. int27 physical configuration packet received received physical configuration packet normally. > reflect to physical register#01(address phy/link - reg 02h) and switch to specified performance automatically. int28 link on packet received received link - on packet addressed to self - node normally. > assert linkon terminal output simultaneously. int29 self - id packet received received self - id packet normally. store data at async receive specific buffer. int30 receive late occurred receive - late was occured. delete packet received. int31 instruction abort (state) though instruction was issued, it was not accepted bec ause the content was not appropriate for this device. e.g.) >issued ? remove sleep ? (02h) instruction in spite of not in sleep condition. >issued ? instruction suspend ? (62h) instruction without instruction to be stopped. >used undefine operand against issue d instruction. >issued instruction was undefined. etc. int32 transmit late occurred transmit - late was occured. >delete packet transmitted.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 1 12 chapter 11 operation this chapter explains the operation of this device and displays the examples of control f low. 11.1. initialization 11.2. self - id packet receiving 11.3. asynchronous packet transmitting 11.4. asynchronous packet receiving 11.5. isochronous packet transmitting 11.6. isochronous packet receiving
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 113 11.1. initialization the example of control flow from the system power on to the packet transmitting/receiving possible state is shown below. in this examle, the device is not operated with cable power supply before turning on the power of system. figure 11.1 example of flow for initialization system power on start internal pll. power cps terminal to ? l ? , up to 500ns. power xreset terminal to ? l ? , up to 400ns. receive bus_reset report bus re set detected(int4) i nterrupt (assert xint). inner reset and release reset. start bus reset process. end read bus reset detected (int4) interrupt. no yes report bus reset complete (int3) i nterrupt (assert xint). read bus reset complete (int3) interr upt. complete bus reset process. packet transmitting/receiving possible start
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 114 11.2. self - id packet receiving the example of control flow for receiving self - id packet is shown below. 11.2.1 self - id packet receive during bus reset process 11.2.2 self - id packet receive after ping packet transmitting
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 115 11.2.1 self - id packet receive at bus reset process this section explains the receiving process of self - id packet. the mb8 6617a device is capable of receiving self - id packets that each mode transmit in the self - identity stage of bus reset process. when ? 1 ? is written to the s - id store bit of mode - control register (refer to 7.1), the self - id packet in the bus reset process ca n be received and the data removing the logical inverse section is stored in the asynchronous receive - fifo and asynchronous transmit - fifo (512 bytes maxixum). when the number of total data exceeds 512 bytes, the overflown data are discarded. bus reset for ce - clears fifo for asynchronous receiving and fifo for asynchronous transmitting to store self - id packet.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 116 < < flow chart before bus reset completion figure 11.2.1.1 flow example for self - id packet receiving before bus reset completion start bus reset. - id store end ? 0 ? report bus reset detected (int4) interrupt. (assert xint) (assert xint). read bus reset detected (int4) interrupt. recv busy bit=0 store received self - id packet to asynchronous receive buffer. report bus reset completed (int3) (assert xint) interrupt. . read bus reset completed (int3) inter rupt. recv busy bit=1 set fifo according to fifo mode. clear asynchronous receive buffer. (note 1) ? 1 ? bus reset completed. yes no bus reset completed . no yes report bus reset completed (int3) interrupt. read bus reset completed (int3) interrupt. end
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 117 < < flow chart after bus reset completion figure 11.2.1.2 flow example for self - id packet receiving after bus reset completed note1: when asyn - fifo sel (mode - control register[3]) is 1 and send/rec (mode - control register [2]) is 1, asynchronous receive fifo (25 6 byte) and bridge fifo (2048 byte) are used with combined as asynchronous receive buffer. in other case, asynchronous receive fifo (256 byte) and asynchronous transmit fifo (256 byte) are used with combined. note2: when asyn - fifo sel is 1 and transmit/rec is 1, asynchronous transmitting fifo (256 byte) and bridge fifo (2048 byt) are cleared, when asyn - fifo sel is 1 and transmit/rec is 0, asynchronous receiving fifo (256 byte) and asynchronous transmitting fifo (256 byte) are cleared. asynchronous transmit fifo and bridge fifo are combined to be set in asynchronous transmit buffer. set asynchronous receive fifo to asynchronous receive buffer. when asyn - fifo sel is 0, asynchronous receive fifo (256 byte) and asynchronous transmit fifo (256 byte) are cleare d and re - set asynchronous receive fifo to asynchronous receive buffer, asynchronous transmit fifo to asynchronous transmit buffer. start issue asynchronous receive (03h) instruction. read one word from receive asynchronous data port. end data req bit read one word of the received data and increment the read poi nter of buffer. recv busy bit=0 issue remove busy (04h) instruction. prepare for reading received data. receive remove busy(04h) instruction. clear the receive asynchronous buffer and set fifo according to fifo mode. (note 2) ? 1 ? read self - id? yes no ? 0 ?
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 118 11.2.2 self - id packet receive after transmitting ping packet ping regardless of s - id store bit setting in the mode - cont rol register (refer to 7.1), the device receives self - id packet after a ping packet transmitted and stores the data removing logical inverse section in the asynchronous receive - fifo. < < flow chart from transmitting of pig packet to receiving self - id packe t ping figure 11.2.2.1 flow example of operation from pin packet transmitting to self - id packet receiving start issue send phy packet(21h) issue instruction. receive transmit phy packet (21h) instruction. read asynchronous transmit buffer. transmit ping packet. arbitration result report physical packet send interrupt (int25) (assert xint). store received self - id packet in asynchronous receive buffer. arbitration procedure end read physical packet send interrupt (in t25) . lost won store ping packet to be transmitted in asynchronous receive buffer. store pin packet (two word) to be transmitted in asynchronous transmit buffer. report self - id packet received interrupt(int29) (assert xint) (xint ) read self - id packet received interrupt (int29) . recv busy=1
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 119 < < flow chart after r eceiving self - id packet figure 11.2.2.2 flow example after receiving self - id packet. start issue asynchronous receive (03h) instruction. read the data of one word from receive asynchronous data port. read flag & status register. end 0 1 data req bit read one word of received data and increment the read pointer of receive buffer. recv busy bit=0 issue remove busy (04h) instruction. prepare for reading received data receive remove busy (04h) instruction. fifo remote mode for receiving completed.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 120 11.3. asynchronous packet transmitting the example of control flow for transmitting of asynchronous packet is shown below. < < flow chart before storing transmitting data into asynchronous transmit fifo figure 11.3.1 flow chart before storing transmitti ng data in asynchronous transmit fifo note1: store the data to be transmit previously in asynchronous transmit fifo. note2: if the transmitting length is below the digit of quadret, write ? 0 ? there up to quadret unit. note3: the device can automatically attaches crc code. start write one word the data to be transmi tted in asynchronous transmit data port. number of residual transfer byte = number of residual transfer byte ? (minus) 2. number of residual transfer byte > 0 end write data for 1 word for asynchronous transmit buffer and increment the write pointer.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 121 < < flow chart after storing transmitting data into asynchronous transmit fifo figure 11.3.2 flow chart after storing transmitting data in asynchronous transmit fifo start issue asynchronous transmit (31h) instruction. receive asynchronous transmit (31h) instruction. read asynchronous transmit buffer. transmit asynchronous packet. arbitration result acknowledge received? report asynchronous packe t send (int17) interrupt (assert xint). report ac knowledge missing (int20) interrupt (assert xint). after the transfer of data_end, release bus and wait asynchronous packet receiving. arbitration procedure end read asynchronous packet transmit (int17) interrupt. read acknowledge missing (int20) interrupt. lost won yes no store receive acknowledge packet in receive ack nowledge indication register.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 122 11.4. asynchronous packet receiving the example of control flow for receiving asynchronous packet is shown below.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 123 < < flow chart for received data before storing in asynchronous receive fifo figure 11.4.1 flow example for received data before storing in asynchronous receive fifo receive packet to self - node. report header crc error(int14) interrupt and duscard received packet. store asynchronous packet into async hronous receive buffer. check header crc. transmit acknowledge packet report asynchronous packet receive (int9) interrupt(assert xint). ng ? 1 ? recv busy bit transmit ? ack_busy_x ? and discard received packet. recv busy bit=1 report asynchronous receive fifo full (int16) interr upt(assert xint). read asynchronous receive fifo full(int16) interrupt. read asynchronous packet received(int9) interrupt. ok read header crc error (int14) interrupt. receive buffer=full ? 0 ? packet receiving process completed packet receiving process completed packet receiving pro cess completed yes no
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 124 < < f low chart for received data after storing in asynchronous receive fifo figure 11.4.2 flow chart for received data after storing in asynchronous receive fifo note1: if the length of received data is below quadret digid, it is stored by quadret unit????. note2: crc code is not included in the data. start issue asynchronous receive(03h) instruction. read 1 word of the data from receive asynchronous data port read flag & status register. end 0 1 data req bit read 1 word of received data and increment read pointer of receive buffer. recv busybit=0 issue remove busy(04h) instruction prepare for reading received data. receive remove busy(04h) instruction. receive fifo read mode completed.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 125 11.5. isochronous packet transmitting the example of control flow for transmitting isochronous packet is shown below.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 126 figure 11.5 flow example for transmitting isochronous packet end set value to registers such as bridge and tspif. set necessary data to registers such as bridg and tspif(note). transmit late evaluation report transmit late occurred (int32) interrupt(assert xint). read transmit late occurred (int32) interrupt. discard source packet and transmit empty packet. transmit late yes no isocycle yes transmit source packet to cp lsi. start store source packet in fifo at tspif. input the source packet data and clock into tspif port. receive processed source packet from cp lsi and store it in fifo at bridge. arbitration result arbitration procedure lost won connect sourc e packet according to register setting and transmit.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 127 (note)register and bit necessary for transmi tting are as follows. data address mpeg - ts dss 00h tspsb=0, cpsb=0 14h,16h set value of transmit offset(ach). 18h,1ah set value of transmit offset (bch) 34h dbsa=06h, fna=3h dbsa=09h, fna=2h 36h txfmta=20h, txcha(iso channel no.) txfmta=21h, txcha( iso channel no.) 38h dbsb=06h, fnb=3h dbsb=09h, fnb=2h 3ah txfmtb=20h, txchb(iso channel no.) txfmtb=21h, txchb(iso channel no.) 40h set criteria for late packet (ach). 42h set criteria for late packet (bch). 10h set at ach transmitting. txsta=1, tfa set at ach transmitting. txsta=1, tfa, txfmta=1, idsizea=1(dss130) 12h set at bch transmitting. txstb=1, tfb set at bch transmitting. txstb=1, tfb, txfmtb=1, idsizeb=1(dss130)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 128 11.6. isochronous packet receiving the example of control flow for receivi ng isochronous packet is shown below. figure 11.6 flow example for transmitting isochronous packet end set value to registers such as bridge and tspif(note). set necessary data to registers such as bridg and tspif. receive late evaluation report receive late occurred(int30) interrupt(assert xint). read receive late occurred (int30) interrupt. discard source packet. receive late yes no transmit source packet to cp lsi. start store source packet in fifo at bridge. receive iso packet. receive processed source packet from cp lsi and store it in fifo at tspif. output source packet from the tspif port when the value of source packet header equals to the val ue of cycle timer.
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 129 (note)register and bit necessary for receiving are as follows. data address mpeg - ts dss dv 00h tspsb=0, cpsb=0 1ch tsen=1, set tv1a,tv1b,tv2a,tv2b according to ch received and port. dssen=1, set tv1a,tv1b,tv2a,tv2b according to ch received and port. dven=1, set tv1a,tv1b,tv 2a,tv2b according to ch received and port. 40h set criteria for late packet (ach). - 42h set criteria for late packet (bch). - 3ch ach received : rxsta=1h, rxcha(iso channel no.) bch received : rxstb=1h, rxchb(iso channel no.)
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 130 chapter 12 system con figuration this chapter explains the system configuration of this chip. 12.1. recommended connection for 1934 port (for one port) 12.2. recommended connection for cable power supply 12.3. recommended connection for build - in pll l oop filter 12.4. configuration of feedback circuit at crystal oscillator
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 131 12.1. recommended connection for 1934 port (for one port) the example of recommended connection of 1934 port terminal for one port is shown below. figure 12.1 recomme nded connection for 1934 port (for one port) for unused 1394 port, tpbias should be open and tpa, xtpa, tpb and xtpb should be be connected to gnd. 1f 56 56 56 56 5.1k 250pf 5.1k1%
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 132 12.2 recommended connection for cable power supply the example of recommended connection of cable power supply for 1394 cable is shown below. figure 12.2 recommended connection for cable power supply 510k w 5% 91 k w 5% cps cable power (max 33v) 2.2uf
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 133 12.3. recommended connection for build - in pll loop filter the example of recommended connection for build - in pll loop filter is s hown below. fil rf figure 12.3 recommended connection for build - in pll loop filter 390 w 5% 3300pf 5% 5.1k w 5%
lsi s pecification MB86617A rev.1.0 fujitsu vlsi 134 12.4. configuration of feedback circuit at crystal oscillator the example of configuration of feedback circuit at crystal oscillator is show n below. no outside resistance is needed because the feedback resistance is built - in.??? figure 12.4 configuration of feedback circuit at crystal oscillator xo xi 20pf 20pf

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